Async.org.uk HomePage (original) (raw)

New to Asynchronous?| Tech. Reports| Tech. Memos| Posters & Presentations| Tools| Chip Gallery| Data and Source Files| People| Our Links| Related Groups & Links| An overview of the group's recent research| Our NCL:µSystems Webpages
Projects

- SONNETS Project2024-2028
"Scalability Oriented Novel Network of Event Triggered Systems" - ESTEEM Project2023-2027
"UKRI-RCN: Exploiting the dynamics of self-timed machine learning hardware" - POETS Project2016-2021
"Event-based parallel computing - partially ordered event-triggered systems" - PRiME Project2013-2018
"Power-efficient, Reliable, Many-core Embedded systems" - SAVVIE Project2012-2016
"Staying alive in variable, intermittent, low-power environments" - UNCOVER Project2012-2015
"UNderstanding COmplex system eVolution through structurEd behaviouRs" - TrAmS Platform Grant2012-2016
"Trustworthy Ambient Systems: Resource Constrained Ambience" - Dream Fellowship2011-2013
"Energy-Modulated Computing" - GAELS Project2011-2014
"Globally Asynchronous Elastic Logic Synthesis" - Holistic Project2009-2013
"Next Generation Energy-Harvesting Electronics: A Holistic Approach"[Theme B Summary] - RelCel Project2009-2012
"Reliable Cell design methods for variable processes"[Final Report] - VERDAD Project2009-2012
"VERification-Driven Asynchronous Design" - SURE Project2007-2010
"SecURE Design Flow"[Final Report] - STEP Project2007-2010
"Self-Timed Event Processor"[Final Report] - SEDATE Project2006-2009
"SElf-timed DATapath synthEsis" - SYRINGE Project2005-2008
"Synchronizer Reliability in the Next Generation of SoC with Multiple Clocks"[Final Report] - NEGUS Project2005-2008
"NExt Generation of interconnection technology for mUltiprocessor Soc"[Final Report] - SCREEN Project - [Publications]2004-2006
"SeCuRE circuit dEsigN"[Final Report] - STELLA Project2003-2006
"Synthesis & TEsting of Low-Latency Asynchronous circuits"[Final Report] - COHERENT Project - [Publications]2001-2004
"COmputational HEteRogEneously timed NeTworks"[Final Report] - BESST Project2001-2004
"Behavioural Synthesis of Systems with Heterogeneous Timing"[Final Report] - MOVIE Project2000-2003
"Model Visualisation for Asynchronous Circuit Design"[Final Report] - BREACH Project2000-2001
"Behavioural REfinements for Asynchronous Circuit syntHesis"[Final Report] - COMFORT Project - [Publications]1998-2001
"asynchronous COmmunication Mechanisms FOr Real-Time systems"[Final Report] - DENT Project1998-2000
"Dependable Embedded system design with petri NeTs" - TIMBRE Project1997-2000
"Time-Predicatable Hardware Platforms"[Final Report] - ASTI Project1997-1999
"Asynchronous Circuit Synthesis and Testing"[Final Report] - HADES Project1996-1999
"Hazard-free Arbiter DESign"[Final Report] - "Asynchronous Circuit Design"1996-1999
- ASAP Project1994-1997
"Automated Synthesis of Synchronous and Asynchronous Parallel Controllers" - "Automated Synthesis of Asynchronous Control Circuits"1994-1995
- "Design of Reliable Asynchronous Controllers and Interfaces"1993-1996
Last modified 10/05/2024 by IGC
