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image/svg+xml Quadruple associative instruction cache 32 KB,128-entry TLB-4K, 7 TLB-2/4M per thread Prefetch buffer (16 bytes) Predecode & instruction length decoder Instruction queue18 x86 instructionsalignmentmacro-op fusion Complexdecoder Simpledecoder Simpledecoder Simpledecoder Decoded instruction queue (28 µ-op entries) micro-op fusion Loopstreamdecoder 2 x register allocation table (RAT) Reorder buffer (128-entry) fused 2 xRetirementregisterfile Reservation station (128-entry) fused Storeaddr.unit AGU Loadaddr.unit AGU Storedata Microinstructionsequencer 256 KB8-way,64 bytescacheline,privateL2-cache 512-entryL2-TLB-4K Integer/MMX ALU,branch SSEADDmove Integer/MMX ALU SSEADDmove FPADD Integer/MMX ALU,2x AGU SSEMUL/DIVmove FPMUL Memory order buffer (MOB) Octuple associative data cache 32 KB,64-entry TLB-4K, 32-entry TLB-2/4M Branchpredictionglobal/bimodal,loop, indirectjmp 128 Port 4 Port 0 Port 3 Port 2 Port 5 Port 1 128 128 128 128 128 Result Bus 256 Quick PathInter-connect DDR3memorycontroller CommonL3-cache8 MB Uncore 4 x 20 Bit6,4 GT/s 3 x 64 Bit1,33 GT/s GT/s: gigatransfers per second Intel Nehalem microarchitecture