High-level synthesis (original) (raw)

dbo:abstract

• High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that takes an abstract behavioral specification of a digital system and finds a register-transfer level structure that realizes the given behavior. Synthesis begins with a high-level specification of the problem, where behavior is generally decoupled from low-level circuit mechanics such as clock-level timing. Early HLS explored a variety of input specification languages, although recent research and commercial applications generally accept synthesizable subsets of ANSI C/C++/SystemC/MATLAB. The code is analyzed, architecturally constrained, and scheduled to transcompile into a register-transfer level (RTL) design in a hardware description language (HDL), which is in turn commonly synthesized to the gate level by the use of a logic synthesis tool. The goal of HLS is to let hardware designers efficiently build and verify hardware, by giving them better control over optimization of their design architecture, and through the nature of allowing the designer to describe the design at a higher level of abstraction while the tool does the RTL implementation. Verification of the RTL is an important part of the process. Hardware can be designed at varying levels of abstraction. The commonly used levels of abstraction are gate level, register-transfer level (RTL), and algorithmic level. While logic synthesis uses an RTL description of the design, high-level synthesis works at a higher level of abstraction, starting with an algorithmic description in a high-level language such as SystemC and ANSI C/C++. The designer typically develops the module functionality and the interconnect protocol. The high-level synthesis tools handle the micro-architecture and transform untimed or partially timed functional code into fully timed RTL implementations, automatically creating cycle-by-cycle detail for hardware implementation. The (RTL) implementations are then used directly in a conventional logic synthesis flow to create a gate-level implementation. (en)
• 高级综合（High-level Synthesis，縮寫 HLS），又譯高层次综合，另又稱C合成（C synthesis）、電子系統層次合成（Electronic System Level synthesis，縮寫 ESL synthesis），是将电路设计规范的算法级或行为级描述在一定的约束条件下转化为描述的方法和过程。高层次综合又称为行为级综合、算法级综合等。它使设计者能够在更高层次进行，更快速有效地在较高层次设计验证和仿真，而较低层次的工作由工具来完成，从而让设计工程师可以有更多的精力和更充分的条件去进行设计空间的搜索，寻求最佳的设计方案。 HLS 的过程通常基本包括、编译、、调度、、控制器、、RTL 、、和反编译等几个部分。编译、转换部分决定了软件的兼容性和易用性，调度（schedule）和分配（binding）主要决定了产生的 RTL 的性能、资源大小等。 (zh)

rdfs:comment

• 高级综合（High-level Synthesis，縮寫 HLS），又譯高层次综合，另又稱C合成（C synthesis）、電子系統層次合成（Electronic System Level synthesis，縮寫 ESL synthesis），是将电路设计规范的算法级或行为级描述在一定的约束条件下转化为描述的方法和过程。高层次综合又称为行为级综合、算法级综合等。它使设计者能够在更高层次进行，更快速有效地在较高层次设计验证和仿真，而较低层次的工作由工具来完成，从而让设计工程师可以有更多的精力和更充分的条件去进行设计空间的搜索，寻求最佳的设计方案。 HLS 的过程通常基本包括、编译、、调度、、控制器、、RTL 、、和反编译等几个部分。编译、转换部分决定了软件的兼容性和易用性，调度（schedule）和分配（binding）主要决定了产生的 RTL 的性能、资源大小等。 (zh)
• High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that takes an abstract behavioral specification of a digital system and finds a register-transfer level structure that realizes the given behavior. Hardware can be designed at varying levels of abstraction. The commonly used levels of abstraction are gate level, register-transfer level (RTL), and algorithmic level. (en)