| dbo:abstract |
LISA (Language for Instruction Set Architectures) is a language to describe the instruction set architecture of a processor. LISA captures the information required to generate software tools (compiler, assembler, instruction set simulator, ...) and implementation hardware (in VHDL or Verilog) of a given processor. LISA has been used to re-implement the hardware of existing processor cores, keeping the binary compatibility with the legacy version, as all software tools did already exist and legacy compiled software images could be executed on the newly created hardware. Another application has been to generate the ISS (instruction set simulator) for RISC processors such the ARM architecture ISSes. LISA is not focused on the modeling of other on-chip components around the processor core itself, such as peripherals, hardware accelerators, buses and memories; Other languages such as SystemC can be used for these. The language has not been yet standardised by IEEE or ISO and is currently owned by RWTH Aachen University, in Germany. (en) |
| dbo:designer |
dbr:Vojin_Zivojnovic,_Stefan_Pees,_version_1.0 |
| dbo:wikiPageExternalLink |
http://www.ice.rwth-aachen.de/research/tools-projects/lisa/lisa http://www.synopsys.com/IP/ProcessorIP/asip/processor-designer/Pages/default.aspx http://www.ice.rwth-aachen.de/fileadmin/publications/Zivojnovic96vlsi.pdf |
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dbr:VHDL dbr:Verilog dbr:Instruction_set_simulator dbr:Compiler dbr:Germany dbr:SystemC dbr:Shaker_Verlag dbr:ARM_architecture dbr:Reconfigurable_computing dbr:International_Organization_for_Standardization dbr:Assembly_language dbc:Specification_languages dbr:Synopsys dbr:IEEE dbr:Instruction_set_architecture dbr:Microprocessor dbr:RWTH_Aachen_University dbr:Reduced_instruction_set_computing dbr:Multi-core dbr:RWTH_Aachen dbr:Parallel_programming dbr:Vojin_Zivojnovic,_Stefan_Pees,_version_1.0 dbr:Alphabetical_list_of_programming_languages dbr:Software_tools dbr:Binary_compatibility |
| dbp:designer |
dbr:Vojin_Zivojnovic,_Stefan_Pees,_version_1.0 |
| dbp:dialects |
LISA 2.0, LISA+ (en) |
| dbp:name |
LISA (en) |
| dbp:website |
http://www.ice.rwth-aachen.de/research/tools-projects/lisa/lisa |
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dbt:Empty_section dbt:ISBN dbt:Infobox_programming_language dbt:More_footnotes dbt:Reflist |
| dbp:year |
1997 (xsd:integer) |
| dcterms:subject |
dbc:Specification_languages |
| gold:hypernym |
dbr:Language |
| rdf:type |
owl:Thing dbo:Language schema:Language wikidata:Q315 wikidata:Q9143 yago:WikicatSpecificationLanguages yago:Abstraction100002137 yago:ArtificialLanguage106894544 yago:Communication100033020 yago:Language106282651 yago:ProgrammingLanguage106898352 dbo:ProgrammingLanguage |
| rdfs:comment |
LISA (Language for Instruction Set Architectures) is a language to describe the instruction set architecture of a processor. LISA captures the information required to generate software tools (compiler, assembler, instruction set simulator, ...) and implementation hardware (in VHDL or Verilog) of a given processor. LISA is not focused on the modeling of other on-chip components around the processor core itself, such as peripherals, hardware accelerators, buses and memories; Other languages such as SystemC can be used for these. (en) |
| rdfs:label |
LISA (Language for Instruction Set Architecture) (en) |
| owl:sameAs |
freebase:LISA (Language for Instruction Set Architecture) yago-res:LISA (Language for Instruction Set Architecture) wikidata:LISA (Language for Instruction Set Architecture) https://global.dbpedia.org/id/4qApR |
| prov:wasDerivedFrom |
wikipedia-en:LISA_(Language_for_Instruction_Set_Architecture)?oldid=787046848&ns=0 |
| foaf:homepage |
http://www.ice.rwth-aachen.de/research/tools-projects/lisa/lisa |
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wikipedia-en:LISA_(Language_for_Instruction_Set_Architecture) |
| foaf:name |
LISA (en) |
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http://www.ice.rwth-aachen.de/research/tools-projects/lisa/lisa |
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dbr:Lisa |
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dbr:LISA_(programming_language) dbr:Language_for_Instruction_Set_Architecture |
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dbr:Lisa dbr:LISA_(programming_language) dbr:Language_for_Instruction_Set_Architecture |
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wikipedia-en:LISA_(Language_for_Instruction_Set_Architecture) |
