MERSI protocol (original) (raw)
The MERSI protocol is a cache coherency and memory coherence protocol used by the PowerPC G4. The protocol consists of five states, Modified (M), Exclusive (E), Read Only or Recent (R), Shared (S) and Invalid (I). The M, E, S and I states are the same as in the MESI protocol. The R state is similar to the E state in that it is constrained to be the only clean, valid, copy of that data in the computer system. Unlike the E state, the processor is required to initially request ownership of the cache line in the R state before the processor may modify the cache line and transition to the M state. In both the MESI and MERSI protocols, the transition from the E to M is silent.
| Property | Value |
|---|---|
| dbo:abstract | The MERSI protocol is a cache coherency and memory coherence protocol used by the PowerPC G4. The protocol consists of five states, Modified (M), Exclusive (E), Read Only or Recent (R), Shared (S) and Invalid (I). The M, E, S and I states are the same as in the MESI protocol. The R state is similar to the E state in that it is constrained to be the only clean, valid, copy of that data in the computer system. Unlike the E state, the processor is required to initially request ownership of the cache line in the R state before the processor may modify the cache line and transition to the M state. In both the MESI and MERSI protocols, the transition from the E to M is silent. For any given pair of caches, the permitted states of a given cache line are as follows: (en) |
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| dbo:wikiPageRevisionID | 678439054 (xsd:integer) |
| dbo:wikiPageWikiLink | dbr:MESI_protocol dbr:PowerPC_G4 dbr:Memory_coherence dbc:Cache_coherency dbr:Cache_coherency |
| dbp:wikiPageUsesTemplate | dbt:Reflist dbt:Y dbt:N |
| dct:subject | dbc:Cache_coherency |
| gold:hypernym | dbr:Coherency |
| rdfs:comment | The MERSI protocol is a cache coherency and memory coherence protocol used by the PowerPC G4. The protocol consists of five states, Modified (M), Exclusive (E), Read Only or Recent (R), Shared (S) and Invalid (I). The M, E, S and I states are the same as in the MESI protocol. The R state is similar to the E state in that it is constrained to be the only clean, valid, copy of that data in the computer system. Unlike the E state, the processor is required to initially request ownership of the cache line in the R state before the processor may modify the cache line and transition to the M state. In both the MESI and MERSI protocols, the transition from the E to M is silent. (en) |
| rdfs:label | MERSI protocol (en) |
| owl:sameAs | freebase:MERSI protocol wikidata:MERSI protocol dbpedia-tr:MERSI protocol https://global.dbpedia.org/id/4qzf5 |
| prov:wasDerivedFrom | wikipedia-en:MERSI_protocol?oldid=678439054&ns=0 |
| foaf:isPrimaryTopicOf | wikipedia-en:MERSI_protocol |
| is dbo:wikiPageWikiLink of | dbr:MESI_protocol dbr:PowerPC_G4 dbr:Cache_coherence dbr:Espresso_(microprocessor) |
| is foaf:primaryTopic of | wikipedia-en:MERSI_protocol |