Memory architecture (original) (raw)
Memory architecture describes the methods used to implement electronic computer data storage in a manner that is a combination of the fastest, most reliable, most durable, and least expensive way to store and retrieve information. Depending on the specific application, a compromise of one of these requirements may be necessary in order to improve another requirement. Memory architecture also explains how binary digits are converted into electric signals and then stored in the memory cells. And also the structure of a memory cell.
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| dbo:abstract | Memory architecture describes the methods used to implement electronic computer data storage in a manner that is a combination of the fastest, most reliable, most durable, and least expensive way to store and retrieve information. Depending on the specific application, a compromise of one of these requirements may be necessary in order to improve another requirement. Memory architecture also explains how binary digits are converted into electric signals and then stored in the memory cells. And also the structure of a memory cell. For example, dynamic memory is commonly used for primary data storage due to its fast access speed. However dynamic memory must be repeatedly refreshed with a surge of current dozens of time per second, or the stored data will decay and be lost. Flash memory allows for long-term storage over a period of years, but it is much slower than dynamic memory, and the static memory storage cells wear out with frequent use. Similarly, the data bus is often designed to suit specific needs such as serial or parallel data access, and the memory may be designed to provide for parity error detection or even error correction. The earliest memory architectures are the Harvard architecture, which has two physically separate memories and data paths for program and data, and the Princeton architecture which uses a single memory and data path for both program and data storage. Most general purpose computers use a hybrid split-cache modified Harvard architecture that appears to an application program to have a pure Princeton architecture machine with gigabytes of virtual memory, but internally (for speed) it operates with an instruction cache physically separate from a data cache, more like the Harvard model. DSP systems usually have a specialized, high bandwidth memory subsystem; with no support for memory protection or virtual memory management.Many digital signal processors have 3 physically separate memories and datapaths -- program storage, coefficient storage, and data storage.A series of multiply–accumulate operations fetch from all three areas simultaneously to efficiently implement audio filters as convolutions. (en) |
| dbo:wikiPageID | 22501335 (xsd:integer) |
| dbo:wikiPageLength | 3840 (xsd:nonNegativeInteger) |
| dbo:wikiPageRevisionID | 1102908621 (xsd:integer) |
| dbo:wikiPageWikiLink | dbr:64-bit dbr:Processor_register dbr:Memory_model_(addressing_scheme) dbr:Memory-disk_synchronization dbr:Memory_protection dbr:Memory_virtualization dbr:Video_memory dbr:Deterministic_memory dbr:ECC_memory dbr:16-bit dbr:Convolution dbr:Modified_Harvard_architecture dbr:Multiply–accumulate_operation dbr:Conventional_memory dbr:Cache-only_memory_architecture dbr:Stack-based_memory_allocation dbr:Lernmatrix dbr:Address_generation_unit dbr:Distributed_memory dbr:Distributed_shared_memory dbr:32-bit dbr:8-bit dbc:Computer_memory dbr:Flash_memory dbr:Flat_memory_model dbr:Non-uniform_memory_access dbr:Memory_refresh dbr:Primary_data_storage dbr:Registered_memory dbr:Harvard_architecture dbr:High_memory_area dbr:Dual-channel_architecture dbr:Universal_memory dbr:Digital_signal_processor dbr:Bus_(computing) dbr:Shared_memory_(interprocess_communication) dbr:Shared_memory_architecture dbr:Cache_memory dbr:Memory_hierarchy dbr:Uniform_memory_access dbr:Virtual_memory dbr:Von_Neumann_architecture dbr:Expanded_memory dbr:Extended_memory dbr:Tagged_architecture dbr:X86_memory_segmentation dbr:Dynamic_memory dbr:PCI_memory_hole dbr:Parity_error dbr:Princeton_architecture dbr:Memory_level_parallelism dbr:Memory_model_(computing) |
| dbp:wikiPageUsesTemplate | dbt:Reflist dbt:Short_description dbt:Computer-stub |
| dct:subject | dbc:Computer_memory |
| gold:hypernym | dbr:Combination |
| rdf:type | dbo:Drug |
| rdfs:comment | Memory architecture describes the methods used to implement electronic computer data storage in a manner that is a combination of the fastest, most reliable, most durable, and least expensive way to store and retrieve information. Depending on the specific application, a compromise of one of these requirements may be necessary in order to improve another requirement. Memory architecture also explains how binary digits are converted into electric signals and then stored in the memory cells. And also the structure of a memory cell. (en) |
| rdfs:label | Memory architecture (en) |
| owl:sameAs | freebase:Memory architecture wikidata:Memory architecture dbpedia-fi:Memory architecture dbpedia-sr:Memory architecture https://global.dbpedia.org/id/Y6tT |
| prov:wasDerivedFrom | wikipedia-en:Memory_architecture?oldid=1102908621&ns=0 |
| foaf:isPrimaryTopicOf | wikipedia-en:Memory_architecture |
| is dbo:wikiPageWikiLink of | dbr:Memory_address dbr:NoRMA dbr:Glossary_of_computer_graphics dbr:Glossary_of_computer_hardware_terms dbr:Distributed_shared_memory dbr:Digital_signal_processor dbr:Direct_Rendering_Manager dbr:Vision_processing_unit dbr:Very_long_instruction_word |
| is foaf:primaryTopic of | wikipedia-en:Memory_architecture |