| dbo:abstract |
Runahead is a technique that allows a microprocessor to pre-process instructions during cache miss cycles instead of stalling. The pre-processed instructions are used to generate instruction and data stream prefetches by detecting cache misses before they would otherwise occur by using the idle execution resources to calculate instruction and data stream fetch addresses using the available information that is independent of the cache miss. The principal hardware cost is a means of checkpointing the register file state and preventing pre-processed stores from modifying memory. This checkpointing can be accomplished using very little hardware since all results computed during runahead are discarded after the cache miss has been serviced, at which time normal execution resumes using the checkpointed register file state. Branch outcomes computed during runahead mode can be saved into a shift register, which can be used as a highly accurate branch predictor when normal operation resumes. Runahead was initially investigated in the context of an in-order microprocessor; however, this technique has been extended for use with out-of-order microprocessors. (en) |
| dbo:wikiPageExternalLink |
http://citeseer.ist.psu.edu/465945.html http://ieeexplore.ieee.org/xpl/freeabs_all.jsp%3Fisnumber=26557&arnumber=1183532 http://portal.acm.org/citation.cfm%3Fid=263597&coll=portal&dl=ACM |
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18019528 (xsd:integer) |
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5661 (xsd:nonNegativeInteger) |
| dbo:wikiPageRevisionID |
1093665014 (xsd:integer) |
| dbo:wikiPageWikiLink |
dbr:Memory_address dbr:Instruction_prefetch dbr:Out-of-order_execution dbr:Shift_register dbr:Branch_predictor dbr:Application_checkpointing dbr:Computer_data_storage dbr:Hardware_register dbr:CPU_cache dbc:Instruction_processing dbr:Data_stream dbr:Hardware_scout dbr:Instruction_(computer_science) dbr:Instruction_set dbr:Microprocessor dbr:Memory_hierarchy dbr:FlashCopy dbr:Register_file dbr:Rock_processor |
| dbp:wikiPageUsesTemplate |
dbt:No_footnotes dbt:Short_description |
| dct:subject |
dbc:Instruction_processing |
| gold:hypernym |
dbr:Technique |
| rdf:type |
dbo:TopicalConcept |
| rdfs:comment |
Runahead is a technique that allows a microprocessor to pre-process instructions during cache miss cycles instead of stalling. The pre-processed instructions are used to generate instruction and data stream prefetches by detecting cache misses before they would otherwise occur by using the idle execution resources to calculate instruction and data stream fetch addresses using the available information that is independent of the cache miss. (en) |
| rdfs:label |
Runahead (en) |
| owl:sameAs |
freebase:Runahead wikidata:Runahead dbpedia-tr:Runahead https://global.dbpedia.org/id/4ubmJ |
| prov:wasDerivedFrom |
wikipedia-en:Runahead?oldid=1093665014&ns=0 |
| foaf:isPrimaryTopicOf |
wikipedia-en:Runahead |
| is dbo:wikiPageWikiLink of |
dbr:Hardware_scout dbr:ARM_Cortex-A77 dbr:Memory-level_parallelism |
| is foaf:primaryTopic of |
wikipedia-en:Runahead |