TILEPro64 (original) (raw)
TILEPro64 és un processador multinucli (anomenat Tile Processor) dissenyat per l'empresa fabless anomenada Tilera. TILEPro64 consisteix d'una xarxa en malla de 64 tiles, on cada tile encapsula un , memòria cache i un encaminador no bloquejant que s'empra per a comunicar-se amb les altres tile.
| Property | Value |
|---|---|
| dbo:abstract | TILEPro64 és un processador multinucli (anomenat Tile Processor) dissenyat per l'empresa fabless anomenada Tilera. TILEPro64 consisteix d'una xarxa en malla de 64 tiles, on cada tile encapsula un , memòria cache i un encaminador no bloquejant que s'empra per a comunicar-se amb les altres tile. (ca) TILEPro64 is a VLIW ISA multicore processor (Tile processor) manufactured by Tilera. It consists of a cache-coherent mesh network of 64 "tiles", where each tile houses a general purpose processor, cache, and a non-blocking router, which the tile uses to communicate with the other tiles on the processor. The short-pipeline, in-order, three-issue cores implement a VLIW instruction set. Each core has a register file and three functional units: two integer arithmetic logic units and a unit. Each of the cores ("tile") has its own L1 and L2 caches plus an overall virtual L3 cache which is an aggregate of all the L2 caches. A core is able to run a full operating system on its own or multiple cores can be used to run a symmetrical multi-processing operating system. TILEPro64 has four DDR2 controllers at up to 800MT/s, two 10-gigabit Ethernet XAUI interfaces, two four-lane PCIe interfaces, and a "flexible" input/output interface, which can be software-configured to handle a number of protocols. The processor is fabricated using a 90 nm process and runs at speeds of 600 to 866 MHz. According to the company, Tilera targets the chip at networking equipment, digital video, and wireless infrastructure markets where the demands for computing processing are high. More recently, Tilera has positioned this processor in the cloud computing space with an 8-processor (512-core) 2U server built by Quanta Computer. TILEPro was supported by the Linux kernel from version 2.6.36 to version 4.16. (en) |
| dbo:thumbnail | wiki-commons:Special:FilePath/Tilera_TILEPro64_BlockDiagram.jpg?width=300 |
| dbo:wikiPageExternalLink | https://web.archive.org/web/20070822233801/http:/www.tilera.com/products/processors.php https://web.archive.org/web/20081203155807/http:/linleygroup.com/npu/Newsletter/wire080924.html%232 https://www.theregister.co.uk/2008/09/23/tilera_cpu_upgrade/ |
| dbo:wikiPageID | 29389039 (xsd:integer) |
| dbo:wikiPageLength | 5461 (xsd:nonNegativeInteger) |
| dbo:wikiPageRevisionID | 1077051863 (xsd:integer) |
| dbo:wikiPageWikiLink | dbr:Processor_register dbr:Router_(computing) dbr:Mesh_network dbr:Memory_controller dbc:Very_long_instruction_word_computing dbr:VLIW dbr:Arithmetic_logic_unit dbr:Linux_kernel dbr:Cache_coherence dbr:Pipeline_(computing) dbr:CPU_cache dbr:Tile_processor dbr:Tilera dbr:6WIND dbr:90_nanometer dbr:DDR2_SDRAM dbr:PCI_Express dbr:PCIe dbr:Kilobyte dbc:Manycore_processors dbc:Computer-related_introductions_in_2008 dbr:TILE64 dbr:Instruction_set dbr:Instruction_set_architecture dbr:Microprocessor dbr:Ethernet dbr:Very_long_instruction_word dbr:Multicore_processor dbr:XAUI dbr:RGMII dbr:File:TILEPro64_TileBlock.JPG dbr:File:Tilera_TILEPro64_BlockDiagram.JPG dbr:Load-store |
| dbp:fastUnit | MHz (en) |
| dbp:fastest | 866 (xsd:integer) |
| dbp:manuf | dbr:Tilera |
| dbp:name | TILEPro64 (en) |
| dbp:numcores | 64 (xsd:integer) |
| dbp:producedStart | 2008 (xsd:integer) |
| dbp:sizeFrom | 90.0 (dbd:nanometre) |
| dbp:slowUnit | MHz (en) |
| dbp:slowest | 600 (xsd:integer) |
| dbp:wikiPageUsesTemplate | dbt:Infobox_CPU |
| dct:subject | dbc:Very_long_instruction_word_computing dbc:Manycore_processors dbc:Computer-related_introductions_in_2008 |
| gold:hypernym | dbr:Processor |
| rdf:type | dbo:Software yago:WikicatMicroprocessors yago:Artifact100021939 yago:Chip103020034 yago:Conductor103088707 yago:Device103183080 yago:Instrumentality103575240 yago:Microprocessor103760310 yago:Object100002684 yago:PhysicalEntity100001930 yago:SemiconductorDevice104171831 yago:Whole100003553 |
| rdfs:comment | TILEPro64 és un processador multinucli (anomenat Tile Processor) dissenyat per l'empresa fabless anomenada Tilera. TILEPro64 consisteix d'una xarxa en malla de 64 tiles, on cada tile encapsula un , memòria cache i un encaminador no bloquejant que s'empra per a comunicar-se amb les altres tile. (ca) TILEPro64 is a VLIW ISA multicore processor (Tile processor) manufactured by Tilera. It consists of a cache-coherent mesh network of 64 "tiles", where each tile houses a general purpose processor, cache, and a non-blocking router, which the tile uses to communicate with the other tiles on the processor. TILEPro was supported by the Linux kernel from version 2.6.36 to version 4.16. (en) |
| rdfs:label | TILEPro64 (ca) TILEPro64 (en) |
| owl:sameAs | freebase:TILEPro64 yago-res:TILEPro64 wikidata:TILEPro64 dbpedia-ca:TILEPro64 https://global.dbpedia.org/id/4vDdY |
| prov:wasDerivedFrom | wikipedia-en:TILEPro64?oldid=1077051863&ns=0 |
| foaf:depiction | wiki-commons:Special:FilePath/TILEPro64_TileBlock.jpg wiki-commons:Special:FilePath/Tilera_TILEPro64_BlockDiagram.jpg |
| foaf:isPrimaryTopicOf | wikipedia-en:TILEPro64 |
| is dbo:computingPlatform of | dbr:Strace |
| is dbo:wikiPageWikiLink of | dbr:Strace dbr:Tile_processor dbr:Tilera dbr:History_of_computing_hardware_(1960s–present) dbr:TILE-Gx dbr:Microprocessor_chronology |
| is foaf:primaryTopic of | wikipedia-en:TILEPro64 |
