TRIPS architecture (original) (raw)

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TRIPS was a microprocessor architecture designed by a team at the University of Texas at Austin in conjunction with IBM, Intel, and Sun Microsystems. TRIPS uses an instruction set architecture designed to be easily broken down into large groups of instructions (graphs) that can be run on independent processing elements. The design collects related data into the graphs, attempting to avoid expensive data reads and writes and keeping the data in high speed memory close to the processing elements. The prototype TRIPS processor contains 16 such elements. TRIPS hoped to reach 1 TFLOP on a single processor, as papers were published from 2003 to 2006.

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dbo:abstract Der TRIPS-Prozessor (Tera-op, Reliable, Intelligently adaptive Processing System) ist ein Forschungsprozessor der University of Texas at Austin. Die Prozessorarchitektur ist so ausgelegt, dass sich weitere Kerne möglichst einfach hinzufügen lassen. Das Projekt wird von IBM und der DARPA gefördert. Die TRIPS-Architektur soll ein Nachfolger der gängigen RISC-Architektur werden und wird als -Architektur bezeichnet. Die EDGE-Architektur weist Blöcke auf, die elementare Anweisungen unabhängig voneinander ausführen, sowie datengesteuerte (out-of-order) Anweisungsausführung. TRIPS wird entwickelt, um Prozessoren mit mehr als einem Teraflop zu realisieren. Auch Intels Terascale-Prozessor wird in diesem Zusammenhang entwickelt, basiert jedoch auf einer anderen Architektur mit gleichartigen Rechenelementen. (de) TRIPS was a microprocessor architecture designed by a team at the University of Texas at Austin in conjunction with IBM, Intel, and Sun Microsystems. TRIPS uses an instruction set architecture designed to be easily broken down into large groups of instructions (graphs) that can be run on independent processing elements. The design collects related data into the graphs, attempting to avoid expensive data reads and writes and keeping the data in high speed memory close to the processing elements. The prototype TRIPS processor contains 16 such elements. TRIPS hoped to reach 1 TFLOP on a single processor, as papers were published from 2003 to 2006. (en) TRIPS (The Tera-op, Reliable, Intelligently adaptive Processing System) è un'architettura per microprocessori sviluppata da un gruppo di ricerca dell'University of Texas at Austin con l'IBM. TRIPS utilizza un nuovo instruction set sviluppato per poter essere suddiviso in blocchi di istruzioni indipendenti in modo da poter essere eseguita da unità di esecuzione indipendenti. Il prototipo del processore basato sull'architettura TRIPS contiene 16 elementi, ma il gruppo di ricerca ritiene di poter facilmente accrescere il parallelismo fino a 128 elementi in un processore utilizzabile per applicazioni reali. Sfruttando le innovazioni portate dalla nuova architettura il team di sviluppo ritiene di poter sviluppare processori in grado di eseguire 1 TeraFlops su singolo integrato entro il 2012. (it) TRIPS (англ. The Tera-op, Reliable, Intelligently adaptive Processing System) — это микропроцессорная архитектура, разработанная командой из Техасского университета в Остине совместно с IBM, Intel и Sun Microsystems. TRIPS использует архитектуру набора команд, разработанную так, чтобы её можно было легко разбить на большие группы инструкций (графиков), которые могут выполняться на независимых элементах обработки. Конструкция собирает связанные данные в графики, пытаясь избежать дорогостоящих операций чтения и записи данных и сохраняя данные в высокоскоростной памяти рядом с элементами обработки. Прототип процессора TRIPS содержит 16 таких элементов. TRIPS надеялся достичь 1 TFLOP на одном процессоре, согласно опубликованным с 2003 по 2006 годы документам. (ru)
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rdfs:comment TRIPS was a microprocessor architecture designed by a team at the University of Texas at Austin in conjunction with IBM, Intel, and Sun Microsystems. TRIPS uses an instruction set architecture designed to be easily broken down into large groups of instructions (graphs) that can be run on independent processing elements. The design collects related data into the graphs, attempting to avoid expensive data reads and writes and keeping the data in high speed memory close to the processing elements. The prototype TRIPS processor contains 16 such elements. TRIPS hoped to reach 1 TFLOP on a single processor, as papers were published from 2003 to 2006. (en) TRIPS (The Tera-op, Reliable, Intelligently adaptive Processing System) è un'architettura per microprocessori sviluppata da un gruppo di ricerca dell'University of Texas at Austin con l'IBM. TRIPS utilizza un nuovo instruction set sviluppato per poter essere suddiviso in blocchi di istruzioni indipendenti in modo da poter essere eseguita da unità di esecuzione indipendenti. Il prototipo del processore basato sull'architettura TRIPS contiene 16 elementi, ma il gruppo di ricerca ritiene di poter facilmente accrescere il parallelismo fino a 128 elementi in un processore utilizzabile per applicazioni reali. Sfruttando le innovazioni portate dalla nuova architettura il team di sviluppo ritiene di poter sviluppare processori in grado di eseguire 1 TeraFlops su singolo integrato entro il 2012. (it) TRIPS (англ. The Tera-op, Reliable, Intelligently adaptive Processing System) — это микропроцессорная архитектура, разработанная командой из Техасского университета в Остине совместно с IBM, Intel и Sun Microsystems. TRIPS использует архитектуру набора команд, разработанную так, чтобы её можно было легко разбить на большие группы инструкций (графиков), которые могут выполняться на независимых элементах обработки. Конструкция собирает связанные данные в графики, пытаясь избежать дорогостоящих операций чтения и записи данных и сохраняя данные в высокоскоростной памяти рядом с элементами обработки. Прототип процессора TRIPS содержит 16 таких элементов. TRIPS надеялся достичь 1 TFLOP на одном процессоре, согласно опубликованным с 2003 по 2006 годы документам. (ru) Der TRIPS-Prozessor (Tera-op, Reliable, Intelligently adaptive Processing System) ist ein Forschungsprozessor der University of Texas at Austin. Die Prozessorarchitektur ist so ausgelegt, dass sich weitere Kerne möglichst einfach hinzufügen lassen. Das Projekt wird von IBM und der DARPA gefördert. Die TRIPS-Architektur soll ein Nachfolger der gängigen RISC-Architektur werden und wird als -Architektur bezeichnet. Die EDGE-Architektur weist Blöcke auf, die elementare Anweisungen unabhängig voneinander ausführen, sowie datengesteuerte (out-of-order) Anweisungsausführung. (de)
rdfs:label TRIPS-Prozessor (de) Architettura TRIPS (it) TRIPS architecture (en) TRIPS (архитектура процессора) (ru)
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