CRAY-1 Hardware Reference Manual (original) (raw)
1.
INTRODUCTION
COMPUTATION SECTION
MEMORY SECTION
INPUT/OUTPUT SECTION
VECTOR PROCESSING
2.
PHYSICAL ORGANIZATION
INTRODUCTION
MAINFRAME
Modules
Printed circuit board
Module assembly
Integrated circuit packages
IC high-speed logic gate
IC slow-speed logic gate
16x1 register chip
10241 memory chip
Resistors
Connector strips
Clock
Power supplies
PRIMARY POWER SYSTEM
COOLING
MAINTENANCE CONTROL UNIT
FRONT-END COMPUTER
EXTERNAL INTERFACE
MASS STORAGE SUBSYSTEM
3.
COMPUTATION SECTION
INTRODUCTION
REGISTER CONVENTIONS
OPERATING REGISTERS
V registers
V register reservations
Vector control registers
VL register
VM register
S registers
T registers
A registers
B registers
FUNCTIONAL UNITS
Address functional units
Address add unit
Address multiply unit
Scalar functional units
Scalar add unit
Scalar shift unit
Scalar logical unit
Population/leading zero count unit
Vector functional units
Vector functional,unit reservation
Recursive characteristic of vector functional units
Vector add unit
Vector shift unit
Vector logical unit
Floating point functional units
Floating point add unit
Floating point multiply unit
Reciprocal approximation unit
ARITHMETIC OPERATIONS
Integer arithmetic
Floating point arithmetic
Normalized floating point
Floating point range errors
Floating point add unit
Floating point multiply unit
Floating point reciprocal approximation unit
Double precision numbers
Addition algorithm
Multiplication algorithm
Division algorithm
LOGICAL OPERATIONS
INSTRUCTION ISSUE AND CONTROL
P register
CIP register
NIP register
LIP register
Instruction buffers
EXCHANGE MECHANISM
XA register
M register
F register
Exchange package
Active exchange package
Exchange sequence
Initiated by dead start sequence
Initiated by interrupt flag set
Initiated by program exit
Exchange sequence issue conditions
Exchange package management
MEMORY FIELD PROTECTION
BA register
LA register
DEAD START SEQUENCE
4.
INSTRUCTIONS
4-1
INSTRUCTION FORMAT
4-1
Arithmetic, logical format
4-1
Shift, mask format
4-2
Immediate constant format
4-2
Memory transfer format
4-3
Branch format
4-4
SPECIAL REGISTER VALUES
4-5
INSTRUCTION ISSUE
4-5
INSTRUCTION DESCRIPTIONS
4-6
000000 Error exit
4-7
001i jk Monitor functions
4-8
0020xk Transmi t (AK) to VL
4-10 2240004 v C
0021xx Set the floating point mode flag in the M register
4-11
0022xx Clear the floating point mode flag in the M register
4-11
003xjx Transmit (Sj) to vector mask
4-12
004xxx Normal exit
4-13
005xjk Branch to (Bjk)
4-14
006ijkm Branch to ijkm
4-15
007ijkm Return jump to ijkm; set Boo to (P)
4-16
010ijkm Branch to ijkm if (Ao) = 0
4-17
011ijkm Branch to ijkm if (Ao) 0
4-17
012ijkm Branch to ijkm if (A0) positive
4-17
013ijkm Branch to ijkm if (Ao) negative
4-17
014ijkm Branch to ijkm if (So) = 0
4-18
015ijkm Branch to ijkm if (So) 0
4-18
016ijkm Branch to ijkm if (So) positive
4-18
017ijkm Branch to ijkm if (So) negative
4-18
0201jkm Transmit j km to Ai
4-19
021ijkm Transmit complement of jkm to Ai
4-19
022ijk Transmit j k to Ai
4-20
023ijx Transmit (Sj) to Ai TD>4-21
024ijk Transmit (Bjk) to Ai
4-22
025ijk Transmit (Ai) to Bjk
4-22
026ijx Population count of (Sj) to Ai
4-23
027ijx Leading zero count of (Sj) to Ai
4-24
030ijk Integer sum of (Aj) and (Ak) to Ai
4-25
031ijk Integer difference (Aj) and (Ak) to Ai
4-25
032ijk Integer product of (Aj) and (Ak) to Ai
4-26
033ijk Transmit I/0 status to Ai
4-27
034ijk Block transfer (Ai) words from memory starting at
address (Ao) to B register starting at register jk
4-29
035ijk Block transfer (Ai) words from B registers starting
at register jk to memory starting at address (Ao)
4-29
036ijk Block transfer (Ai) words from memory starting at
address (Ao) to T registers starting at register jk
4-29
037ijk Block transfer (Ai) words from T registers starting
at register jk to memory starting at address (Ao)
4-29 2240004 vi
C
040ijkm Transmit jkm to Si
4-31
041ijkm Transmit complement of jkm to Si
4-31
042ijk Form 64-jk bits of one's mask in Si from right
4-32
043ijk Form jk bits of one's mask in Si from left
4-32
044ijk Logical product of (Sj) and (Sk) to Si
4-33
045ijk Logical product of (Sj) and complement of Sk to Si
4-33
046ijk Logical difference of (Sj) and (Sk) to Si
4-33
047ijk Logical difference of (Sk) and complement of Sk) to Si
4-33
050i j k Scalar merge
4-33
051ijk Logical sum of (Sj) and (Sk) to Si
4-33
052ijk Shift (Si) left jk places to So
4-36
053ijk Shift (Si) right 64-jk places to So
4-36
054ijk Shift (Si) left jk places to Si
4-36
055ijk Shift (Si) right 64-jk places to Si
4-36
056ijk Shift (Si) and (Sj) left by (Sk) places to Si
4-37
057ijk Shift (Sj) and (Si) right by (Ak) places to Si
4-37
060ijk Integer sum of (Sj) and (Sk) to Si
4-38
061ijk Integer difference of (Sj) and (Sk) to Si
4-38
062ijk Floating sum of (Sj) and (Sk) to Si
4-39
063ijk Floating difference of (Sj) and (Sk) to Si
4-39
064ijk Floating product of (Sj) and (Sk) to Si
4-40
065ijk Half-precision rounded floating product of (Sj) and (Sk) to Si
4-40
066ijk Rounded floating product of (Sj) and (Sk) to Si
4-40
067ijk Reciprocal iteration; 2-(Sj)*(Sk) to Si
4-40
070ijx Floating reciprocal approximation of (Sj) to Si
4-42
071ijk Transmit (Ak) or normalized floating point constant to Si
4-43
072ixx Transmit (RTC) to Si
4-45
073ixx Transmit (VM) to Si
4-45
074ijk Transmit (Tjk) to Si
4-45
075ijk Transmit (Si) to Tjk
4-45
076ijk Transmit (Vj element (Ak)) to Si
4-46
077ijk Transmit (SP to Vi element (Ak)
4-46 2240004 vii C
10hijkm Read from ((Ah) + jkm) to Ai
4-47
11hijkm Store (Ai) to (Ah) + jkm
4-47
12hijkm Read from ((Ah) + jkm) to Si
4-47
13hijkm Store (Si) to (Ah) + jkm
4-47
140ijk Logical products of (Sj) and (Vk elements) to Vi elements
4-49
141ijk Logical products of (Vj elements) and (Vk elements to Vi elements
4-49
142ijk Logical sums of (Sj) and (Vk elements) to Vi elements
4-49
143ijk Logical sums of (Vj elements) and (Vk elements) to Vi elements
4-49
144ijk Logical differences of (Sj) and (Vk elements) to Vi elements
4-49
145ijk Logical differences of (Vj elements) and (Vk elements) to Vi elements
4-49
146ijk If VM bit = 1, transmit (Sj) to Vi elements
If VM bit 1, transmit (Vk elements) to Vi elements
4-49
147ijk If VM bit = 1, transmit (Vj elements) to Vi elements
If VM bit 1, transmit (Vk elements) to Vi elements
4-49
150ijk Single shift of (Vj elements) left by (Ak) places to Vi elements
4-53
151ijk Single shift of (Vi elements) right by (Ak) places to Vi elements
4-53
152ijk Double shifts of (Vj elements) left (Ak) places to Vi elements
4-54
153ijk Double shifts of (Vj elements) right (Ak) places to Vi elements
4-54
154ijk Integer sums (Sj) and (Vk elements) to Vi elements 4-59
155ijk Integer sums (Vj elements) and (Vk elements) to Vi elements
4-59
156ijk Integer differences of (Sj) and (Vk elements) to Vi elements
4-59
157ijk Integer differences of (Vj elements) and (Vk elements) to Vi elements
4-59 2240004 viii
APPENDIXES
A TIMING SUMMARY
A-1
B MODULE TYPES
B-1
C SOFTWARE CONSIDERATIONS
C-1
D INSTRUCTION SUMMARY
D-1
FIGURES
1-1 Basic computer system
2-1 Physical organization of the mainframe
2-2 General chassis layout
2-3 Clock pulse waveform
3-1 Computation section
3-2 Integer data formats
3-3 Floating point data format
3-4 49-bit floating point addition
3-5 Floating point multiply pyramid
3-6 Relationship of instruction buffers and registers
3-7 Instruction buffers
3-8 Exchange package
4-1 General format for instructions
4-1
4-2 Format for arithmetic and logical instructions
4-2
4-3 Format for shift and mask instructions
4-2
4-4 Format for immediate constant instructions
4-3
4-5 Format for memory transfer instructions
4-4
4-6 Two-parcel format for branch instructions
4-4
5-1 Memory organization
5-2
5-2 Memory address
5-3
6-1 Channel I/0 control
6-2
TABLES
1-1 Characteristics of CRAY-1 Computer System
2-1 Characteristics of a DD-19 Disk Storage Unit