Real-Time and Embedded Systems Lab (original) (raw)

Seminar on Resource Sharing in Real-Time Systems

Organizers

Jan Reineke, Andreas Abel

Registration

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Organization

| Language: | English | | | -------------------- | ------------------------------------------------------------------------ | | | Participants: | 12 seats | | | Preparatory Meeting: | Thursday, 2015-10-22, 14:00 - 16:00 pm (sine tempore), E1.3, room SR 014 | | | Weekly Meeting: | Thursdays, 14:00 - 16:00 pm (sine tempore), E1.3 room SR 014 | |

Synopsis

Multi-processor and multi-core architectures use a combination of private and shared resources, to achieve high average-case performance at low implementation cost.

Resource sharing leads to resource contention, as several threads/tasks compete for one resource. Resource contention degrades performance. It also makes performance prediction difficult.

In this seminar, we will study recent work in the context of real-time systems to reduce, and/or analyze contention on shared resources.

Seminar Structure

During the semester we will meet once a week, each time discussing two papers. The discussion of each paper will start with a 30-minute presentation by one of the participants. In addition to the presenter, two students (in the following referred to as discussants) will prepare questions for each paper to aid the discussion.

The presenter and the two discussants should write a short, one-page summary of the week's paper including open questions and submit it to their advisor at least one week before the corresponding meeting.

Presenters should meet with their advisor at least two weeks prior to their presentation. They should provide a draft of their presentation to the advisor prior to their meeting.

At the end of the semester, we will reconvene for a colloquium. Based on the feedback received during the semester each student will again present his paper, this time in the context of all the work discussed in the seminar. Each participant should also deliver a 5-page summary of his assigned paper by the end of March 2016. The following LaTeX template should be used for the summary: <template.tex>

Schedule

Slides

• to be added

Literature (partially for download only within university network)

Shared Main Memory

1. J. Reineke, I. Liu, H. D. Patel, S. Kim, E. A. Lee: PRET DRAM Controller: Bank Privatization for Predictability and Temporal Isolation, CODES+ISSS, 2011
2. L. Ecco, S. Tobuschat, S. Saidi, R. Ernst: A mixed critical memory controller using bank privatization and fixed priority scheduling, RTCSA, 2014
3. H. Yun, R. Mancuso, Z. Wu, R. Pellizzoni: PALLOC: DRAM Bank-aware Memory Allocator for Performance Isolation on Multicore Platforms, RTAS, 2014
4. H. Kim, D. Broman, E. A. Lee, M. Zimmer, A. Shrivastava and J. Oh: A Predictable and Command-Level Priority-Based DRAM Controller for Mixed-Criticality Systems, RTAS, 2015

Shared Caches

1. B. Ward, J. Herman, C. Kenna, and J. Anderson: Making Shared Caches More Predictable on Multicore Platforms, ECRTS, 2013
2. K. Nagar, Y. Srikant: Precise Shared Cache Analysis Using Optimal Interference Placement, RTAS, 2014
3. H. Kim, A. Kandhalu, R. Rajkumar: A Coordinated Approach for Practical OS-Level Cache Management in Multi-core Real-Time Systems, ECRTS, 2013
4. R. Mancuso, R. Dudko, E. Betti, M. Cesati, M. Caccamo, R. Pellizzoni: Real-time cache management framework for multi-core architectures, RTAS, 2013

Other

1. H. Yun, G. Yao, R. Pellizzoni, M. Caccamo, L. Sha: MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms, RTAS, 2013
2. B. Akesson, A. Minaeva, P. Sucha, A. Nelson, Z. Hanzalek: An Efficient Configuration Methodology for Time-Division Multiplexed Single Resources, RTAS, 2015
3. S. Altmeyer, R. Douma, W. Lunniss, R.I. Davis: Evaluation of Cache Partitioning for Hard Real-Time Systems, ECRTS, 2014
4. A. Wieder, B. Brandenburg: On Spin Locks in AUTOSAR: Blocking Analysis of FIFO, Unordered, and Priority-Ordered Spin Locks, RTSS, 2013