SSE3 (original) (raw)

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CPU instruction set

Not to be confused with SSSE3.

SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI),[1] is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revision of their Pentium 4 CPU.[1] In April 2005, AMD introduced a subset of SSE3 in revision E (Venice and San Diego) of their Athlon 64 CPUs.[2] The earlier SIMD instruction sets on the x86 platform, from oldest to newest, are MMX, 3DNow! (developed by AMD, no longer supported on newer CPUs), SSE, and SSE2.

SSE3 contains 13 new instructions over SSE2.[3]

The most notable change is the capability to work horizontally in a register, as opposed to the more or less strictly vertical operation of all previous SSE instructions. More specifically, instructions to add and subtract the multiple values stored within a single register have been added.[4] These instructions can be used to speed up the implementation of a number of DSP and 3D operations. There is also a new instruction to convert floating point values to integers without having to change the global rounding mode, thus avoiding costly pipeline stalls. Finally, the extension adds LDDQU, an alternative misaligned integer vector load that has better performance on NetBurst based platforms for loads that cross cacheline boundaries.[5]

• AMD:
  • Opteron (since Stepping E4[6])
  • Sempron (since Palermo. Stepping E3)
  • Athlon 64 (since Venice Stepping E3 and San Diego Stepping E4)
  • Athlon 64 FX (since San Diego Stepping E4)
  • Athlon 64 X2
  • Phenom 64 X2
  • Turion family
  • K10 family
  • APU family (including without GPU)
  • FX Series
  • Zen family
• Intel:
  • Celeron D
  • Celeron (starting with Core microarchitecture)
  • Pentium 4 (since Prescott)
  • Pentium D
  • Pentium Extreme Edition (but NOT Pentium 4 Extreme Edition)
  • Pentium Dual-Core
  • Pentium (starting with Core microarchitecture)
  • Core
  • Xeon (since Nocona[7])
  • Atom
• VIA/Centaur:
  • C7
  • Nano
• Transmeta Efficeon TM88xx (NOT Model Numbers TM86xx)

Common instructions

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ADDSUBPD

Add-Subtract-Packed-Double[8]

• Input: { A0, A1 }, { B0, B1 }
• Output: { A0 − B0, A1 + B1 }

ADDSUBPS

Add-Subtract-Packed-Single[8]

• Input: { A0, A1, A2, A3 }, { B0, B1, B2, B3 }
• Output: { A0 − B0, A1 + B1, A2 − B2, A3 + B3 }

AOS ( Array Of Structures )

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HADDPD

Horizontal-Add-Packed-Double[8]

• Input: { A0, A1 }, { B0, B1 }
• Output: { A0 + A1, B0 + B1 }

HADDPS

Horizontal-Add-Packed-Single[8]

• Input: { A0, A1, A2, A3 }, { B0, B1, B2, B3 }
• Output: { A0 + A1, A2 + A3, B0 + B1, B2 + B3 }

HSUBPD

Horizontal-Subtract-Packed-Double[8]

• Input: { A0, A1 }, { B0, B1 }
• Output: { A0 − A1, B0 − B1 }

HSUBPS

Horizontal-Subtract-Packed-Single[8]

• Input: { A0, A1, A2, A3 }, { B0, B1, B2, B3 }
• Output: { A0 − A1, A2 − A3, B0 − B1, B2 − B3 }

LDDQU

As stated above, this is an alternative misaligned integer vector load.[8] It can be helpful for video compression tasks.

[MOVDDUP](/wiki/MOVDDUP "MOVDDUP"), MOVSHDUP, MOVSLDUP[4]

These are useful for complex numbers and wave calculation like sound.

FISTTP

Like the older x87 FISTP instruction, but ignores the floating point control register's rounding mode settings and uses the "chop" (truncate) mode instead.[4] Allows omission of the expensive loading and re-loading of the control register in languages such as C where float-to-int conversion requires truncate behaviour by standard.

MONITOR, MWAIT

The MONITOR instruction is used to specify a memory address for monitoring, while the MWAIT instruction puts the processor into a low-power state and waits for a write event to the monitored address.[4]

1. ^ a b Shimpi, Anand Lal; Wilson, Derek. "Intel's Pentium 4 E: Prescott Arrives with Luggage". www.anandtech.com. Retrieved 2023-04-10.
2. ^ Shimpi, Anand Lal. "Industry Update - Q4-2004: AMD adds SSE3 Support, Intel's 925/915 not selling and more". www.anandtech.com. Retrieved 2023-04-10.
3. ^ "Intel Instruction Set Extensions Technology". Intel. Retrieved 2023-04-10.
4. ^ a b c d Wright, Christopher. "SSE3 Instruction Set". softpixel.com. Retrieved 2023-04-10.
5. ^ "LDDQU — Load Unaligned Integer 128 Bits". www.felixcloutier.com. Retrieved 2023-04-10.
6. ^ Wilson, Derek. "AMD K8 E4 Stepping: SSE3 Performance". www.anandtech.com. Retrieved 2023-04-10.
7. ^ "Intel Xeon 3.4GHz ['Nocona' core]". HEXUS. 2004-08-18. Retrieved 2023-04-10.
8. ^ a b c d e f g "SSE3 Instructions - x86 Assembly Language Reference Manual". docs.oracle.com. Retrieved 2023-04-10.

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