How to square floats accurately and efficiently on the ST231 integer processor (original) (raw)
Pré-Publication, Document De Travail Année : 2010
Résumé
We consider the problem of computing IEEE floating-point squares by means of integer arithmetic. We show how the specific properties of squaring can be exploited in order to design and implement algorithms that have much lower latency than those for general multiplication, while still guaranteeing correct rounding. Our algorithm descriptions are parameterized by the floating-point format, aim at high instruction-level parallelism (ILP) exposure, and cover all rounding modes. We show further that their C implementation for the binary32 format yields efficient codes for targets like the ST231 VLIW integer processor from STMicroelectronics, with a latency at least 1.75x smaller than that of general multiplication in the same context.
Mots clés
- Squaring
- Binary floating-point arithmetic
- Correct rounding
- IEEE 754
- Instruction level parallelism
- C software implementation
- VLIW integer processor
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https://ens-lyon.hal.science/ensl-00532829
Soumis le : vendredi 19 novembre 2010-07:00:22
Dernière modification le : vendredi 24 octobre 2025-17:40:02
Archivage à long terme le : vendredi 26 octobre 2012-16:00:13
Dates et versions
ensl-00532829 , version 1 (19-11-2010)
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Identifiants
- HAL Id : ensl-00532829 , version 1
Citer
Claude-Pierre Jeannerod, Jingyan Jourdan-Lu, Christophe Monat, Guillaume Revy. How to square floats accurately and efficiently on the ST231 integer processor. 2010. ⟨ensl-00532829⟩
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