(original) (raw)
Hi Tim,
Thank you a lot for your reply. So IIUC, optimization passes in opt do not reorder IR instructions, only passes in llc that move MIR instructions around. Is it correct?
On the back-end (llc) side, hasSideEffects might prevent some reordering. But I just learn about TargetInstrInfo::isSchedulingBoundary. Can you tell me what are the differences between the two please?
Thank you very much (again),
Son Tuan Vu
On Mon, Sep 17, 2018 at 12:13 PM Tim Northover <t.p.northover@gmail.com> wrote:
Hi,
On Sun, 16 Sep 2018 at 22:02, Son Tuan VU via llvm-dev
<llvm-dev@lists.llvm.org> wrote:
\> I want to add a custom intrinsic to the LLVM IR which would be lowered into a pseudo instruction since it doesn't correspond to any real instruction defined by the architecture. The speciality of this intrinsic/pseudo instruction that it should behave like a scheduling barrier: every instruction before the intrinsic has to be emitted before the intrinsic, the same goes for all instructions after the intrinsic, and this should hold after any optimization in opt and llc.
That's going to be very difficult. LLVM allows intrinsics to have
unmodelled side-effects that prevent reordering with instructions that
might also have side-effects (including loads and stores). But it
assumes that simple arithmetic instructions (like "add") have no
effect other than what's in the IR so they can be freely moved past
anything.
The difference occasionally comes up when people want begin-benchmark
and end-benchmark intrinsics, but really the whole concept of what's
calculated between two points is pretty fuzzy.
\> Which bit should be set to 1? isBarrier or hasSideEffects or both?
hasSideEffects is the closest, with the caveats above.
isBarrier has nothing to do with fences. It's applied to unconditional
branches so that LLVM knows that a basic-block ending with that
instruction won't fall-through.
Cheers.
Tim.