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Hi,

On 1/31/19 11:20 PM, Jacob Lifshay wrote:

We're in-progress designing a RISC-V extension (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-January/000433.html) that would have variable-length vectors of short vectors (1 to 4):

>

where each predicate bit masks out a whole short vector. We're using this extension to vectorize graphics code where where variables in the pre-vectorization code are short vectors.

So, vectorizing code like:

for(int i = 0; i < 1000; i++)

{

vec4 color = colors\[i\];

vec3 normal = normals\[i\];

color.rgb \*= fmax(0.0, dot(normal, light\_dir));

colors\[i\] = color;

}

I'm planning on passing already vectorized code into LLVM and using LLVM as a backend for optimization and JIT code generation.

Do you think the EVL proposal would support an ISA like this as it's currently written (by pattern matching on predicate expansion and vector-length multiplication)?

Or, do you think the EVL proposal would need modification to effectively support this (by adding a element group size argument to EVL intrinsics or something)?

We could untie the mask length from the data length:

%result = call @llvm.evl.fsub.v4f32( %x, %y, %M, i32 %L)

would then indicate the the mask %M applies to groups of "4 / 1" float elements.