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Hello Team,

I have the following question relate to how to associate multiple SchedWriteRes with the same schedule model to a particular instruction.

For AArch64 target, at line , we have

def KryoWrite\_3cyc\_XY\_noRSV\_163ln :
SchedWriteRes<\[KryoUnitXY\]> {
let Latency = 3; let NumMicroOps = 2;}

def : InstRW<\[KryoWrite\_3cyc\_XY\_noRSV\_163ln\],
(instregex "(S|U)QXTU?N(v16i8|v8i16|v4i32|v8i8|v4i16|v2i32)")>;

Similarly, at line ,

def KryoWrite\_1cyc\_XY\_noRSV\_215ln :
SchedWriteRes<\[KryoUnitXY\]> {
let Latency = 1; let NumMicroOps = 2;
}
def : InstRW<\[KryoWrite\_1cyc\_XY\_noRSV\_215ln\],
(instregex "XTNv.\*")>;

Both the InstRW records can match instruction SQXTNv16i8 and both have SchedModel == KryoModel (because of this).

However, the corresponding SchedWriteRes'es have different latencies. I am not sure which one of the two SchedWriteRes are going to be applied for the matched instruction.

Another similar situation: There are other cases like in lines here and here

def KryoWrite\_1cyc\_LS\_Y\_XY\_305ln :
SchedWriteRes<\[KryoUnitLS, KryoUnitY, KryoUnitXY\]> {
let Latency = 1; let NumMicroOps = 3;
}
def : InstRW<\[WriteAdr, KryoWrite\_1cyc\_LS\_Y\_XY\_305ln\],
(instregex "ST1(One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))\_POST$")>;

def KryoWrite\_1cyc\_LS\_Y\_X\_301ln :
SchedWriteRes<\[KryoUnitLS, KryoUnitY, KryoUnitX\]> {
let Latency = 1; let NumMicroOps = 3;
}
def : InstRW<\[WriteAdr, KryoWrite\_1cyc\_LS\_Y\_X\_301ln\],
(instregex "ST1(One(v8b|v4h|v2s|v1d|v16b|v8h|v4s|v2d)|(i8|i16|i32|i64)|Two(v8b|v4h|v2s|v1d))\_POST$")>;

Both match ST1Twov2s\_POST both have SchedModel == KryoModel, but the corresponding SchedSriteRes have different proc resources. Again, not sure which one to consider for the matched instruction.

Thanks,

Sandeep Dasgupta