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Hello

Could somebody clarify how pipeline class is applied on sequence of instructions in architecture description file? For instance, class ialu\_reg on countLeadingZerosL\_bsr (snippet is below) or ialu\_reg\_mem on loadUB2L\_immI (all from x86\_64.ad).

Stages for arguments read/writes, decoder and execution unit are specified only once. Is it then applied on every instructions that uses that pipeline class arguments or for the whole ins\_encode body?

BTW countLeadingZerosL\_bsr isn’t even a “single\_instruction”.

Class pipe\_cmplt looks more reasonable, but and\_cmpLTMask and cadd\_cmpLTMask still don’t have 4 instructions how it is defined. Why 4 cycles are allocated to decode?

Thanks,

Alexander

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// Integer ALU reg operation

pipe\_class ialu\_reg(rRegI dst)

%{

single\_instruction;

dst : S4(write);

dst : S3(read);

DECODE : S0; // any decoder

ALU : S3; // any alu

%}

instruct countLeadingZerosL\_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{

predicate(!UseCountLeadingZerosInstruction);

match(Set dst (CountLeadingZerosL src));

effect(KILL cr);

format %{ "bsrq dst,dst, dst,src\\t# count leading zeros (long)\\n\\t"

"jnz skip\\n\\t"

"movl $dst, -1\\n"

"skip:\\n\\t"

"negl $dst\\n\\t"

"addl $dst, 63" %}

ins\_encode %{

Register Rdst = dstdstdst$Register;

Register Rsrc = srcsrcsrc$Register;

Label skip;

\_\_ bsrq(Rdst, Rsrc);

\_\_ jccb(Assembler::notZero, skip);

\_\_ movl(Rdst, -1);

\_\_ bind(skip);

\_\_ negl(Rdst);

\_\_ addl(Rdst, BitsPerLong - 1);

%}

ins\_pipe(ialu\_reg);

%}