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module inv_testbench; reg astim; wire bmon; inv DUT ( .a(astim), .b(bmon) ); initial begin astim = 0; display("display("%b -> %b", astim, bmon); #10 astim = 1; display("display("%b -> %b", astim, bmon); #30 astim = 0; display("display("%b -> %b", astim, bmon); #20 display("finish; end endmodule