(original) (raw)

{"entities":{"Q827773":{"pageid":780548,"ns":0,"title":"Q827773","lastrevid":2286497457,"modified":"2024-12-12T19:02:08Z","type":"item","id":"Q827773","labels":{"zh-hans":{"language":"zh-hans","value":"Verilog"},"zh-hant":{"language":"zh-hant","value":"Verilog"},"zh-hk":{"language":"zh-hk","value":"Verilog"},"pt":{"language":"pt","value":"Verilog"},"pl":{"language":"pl","value":"Verilog"},"he":{"language":"he","value":"Verilog"},"fr":{"language":"fr","value":"Verilog"},"ko":{"language":"ko","value":"\ubca0\ub9b4\ub85c\uadf8"},"ru":{"language":"ru","value":"Verilog"},"hy":{"language":"hy","value":"\u054e\u0565\u0580\u056b\u056c\u0578\u0563"},"es":{"language":"es","value":"Verilog"},"en":{"language":"en","value":"Verilog"},"tr":{"language":"tr","value":"Verilog"},"ro":{"language":"ro","value":"Verilog"},"ca":{"language":"ca","value":"Verilog"},"hu":{"language":"hu","value":"Verilog"},"it":{"language":"it","value":"Verilog"},"de":{"language":"de","value":"Verilog"},"ja":{"language":"ja","value":"Verilog"},"cs":{"language":"cs","value":"Verilog"},"sv":{"language":"sv","value":"Verilog"},"nl":{"language":"nl","value":"Verilog"},"uk":{"language":"uk","value":"Verilog"},"zh":{"language":"zh","value":"Verilog"},"scn":{"language":"scn","value":"Verilog"},"et":{"language":"et","value":"Verilog"},"nn":{"language":"nn","value":"Verilog"},"da":{"language":"da","value":"Verilog"},"fi":{"language":"fi","value":"Verilog"},"sr":{"language":"sr","value":"\u0412\u0435\u0440\u0438\u043b\u043e\u0433"},"wuu":{"language":"wuu","value":"Verilog"},"vi":{"language":"vi","value":"Verilog"},"nb":{"language":"nb","value":"Verilog"},"ar":{"language":"ar","value":"\u0641\u064a\u0631\u064a\u0644\u0648\u062c (\u0628\u0631\u0645\u062c\u0629)"},"fa":{"language":"fa","value":"\u0648\u0631\u06cc\u0644\u0648\u06af"},"vec":{"language":"vec","value":"Verilog"},"ga":{"language":"ga","value":"Verilog"},"is":{"language":"is","value":"Verilog"},"syl":{"language":"syl","value":"\ua81c\ua826\ua81e\ua824\ua81f\ua809"}},"descriptions":{"en":{"language":"en","value":"hardware description language"},"uk":{"language":"uk","value":"\u041c\u043e\u0432\u0430 \u043e\u043f\u0438\u0441\u0443 \u0430\u043f\u0430\u0440\u0430\u0442\u0443\u0440\u0438 (\u0434\u043b\u044f \u0432\u0435\u0440\u0438\u0444\u0456\u043a\u0430\u0446\u0456\u0457 \u0442\u0430 \u0441\u0438\u043d\u0442\u0435\u0437\u0443)."},"scn":{"language":"scn","value":"linguaggiu di discrizzioni hardware"},"de":{"language":"de","value":"Hardwarebeschreibungssprache"},"fr":{"language":"fr","value":"langage de description de mat\u00e9riel"},"es":{"language":"es","value":"lenguaje de programaci\u00f3n"},"it":{"language":"it","value":"linguaggio di descrizione dell'hardware"},"ml":{"language":"ml","value":"\u0d2a\u0d4d\u0d30\u0d4b\u0d17\u0d4d\u0d30\u0d3e\u0d2e\u0d3f\u0d19\u0d4d \u0d2d\u0d3e\u0d37"},"hi":{"language":"hi","value":"\u092a\u094d\u0930\u094b\u0917\u094d\u0930\u093e\u092e\u093f\u0902\u0917 \u092d\u093e\u0937\u093e"},"pa":{"language":"pa","value":"\u0a2a\u0a4d\u0a30\u0a4b\u0a17\u0a30\u0a3e\u0a2e\u0a3f\u0a70\u0a17 \u0a2d\u0a3e\u0a38\u0a3c\u0a3e"},"pt":{"language":"pt","value":"linguagem de programa\u00e7\u00e3o"},"ro":{"language":"ro","value":"limbaj de programare"},"sv":{"language":"sv","value":"programspr\u00e5k"},"nn":{"language":"nn","value":"programmeringsspr\u00e5k"},"da":{"language":"da","value":"programmeringssprog"},"nl":{"language":"nl","value":"programmeertaal"},"fi":{"language":"fi","value":"ohjelmointikieli"},"pl":{"language":"pl","value":"j\u0119zyk programowania"},"cs":{"language":"cs","value":"programovac\u00ed jazyk"},"sk":{"language":"sk","value":"programovac\u00ed jazyk"},"ca":{"language":"ca","value":"llenguatge de programaci\u00f3"},"he":{"language":"he","value":"\u05e9\u05e4\u05ea \u05ea\u05db\u05e0\u05d5\u05ea"},"ja":{"language":"ja","value":"\u96fb\u5b50\u56de\u8def\u3092\u8a2d\u8a08\u3059\u308b\u30cf\u30fc\u30c9\u30a6\u30a7\u30a2\u8a18\u8ff0\u8a00\u8a9e"},"br":{"language":"br","value":"yezh programmi\u00f1"}},"aliases":{"zh":[{"language":"zh","value":"Verilog HDL"},{"language":"zh","value":"IEEE 1364"}],"he":[{"language":"he","value":"\u05d5\u05e8\u05d9\u05dc\u05d5\u05d2"}],"ja":[{"language":"ja","value":"VerilogHDL"},{"language":"ja","value":"IEEE 1364"},{"language":"ja","value":"Verilog HDL"},{"language":"ja","value":"Verilog-HDL"}],"en":[{"language":"en","value":"Verilog HDL"},{"language":"en","value":"IEEE 1364"}],"uk":[{"language":"uk","value":"Verilog HDL"}],"ca":[{"language":"ca","value":"IEEE 1364"}]},"claims":{"P31":[{"mainsnak":{"snaktype":"value","property":"P31","hash":"69826d6175779989aa65a0ba7574caea95b6e24c","datavalue":{"value":{"entity-type":"item","numeric-id":173341,"id":"Q173341"},"type":"wikibase-entityid"},"datatype":"wikibase-item"},"type":"statement","id":"Q827773$5748f754-41ba-ae03-5323-043a4f7bf78e","rank":"normal"},{"mainsnak":{"snaktype":"value","property":"P31","hash":"ae315e2737875baa2c6468050f82a97e82bdd0df","datavalue":{"value":{"entity-type":"item","numeric-id":1941921,"id":"Q1941921"},"type":"wikibase-entityid"},"datatype":"wikibase-item"},"type":"statement","id":"Q827773$AAEF423A-55BF-493A-8196-A2D7D247149A","rank":"normal"}],"P646":[{"mainsnak":{"snaktype":"value","property":"P646","hash":"4da5735e9211f2ab7e583989831b6e0285c222e6","datavalue":{"value":"/m/0h3vb","type":"string"},"datatype":"external-id"},"type":"statement","id":"Q827773$D995A748-7869-4370-97CA-9572866B7227","rank":"normal","references":[{"hash":"2b00cb481cddcac7623114367489b5c194901c4a","snaks":{"P248":[{"snaktype":"value","property":"P248","hash":"a94b740202b097dd33355e0e6c00e54b9395e5e0","datavalue":{"value":{"entity-type":"item","numeric-id":15241312,"id":"Q15241312"},"type":"wikibase-entityid"},"datatype":"wikibase-item"}],"P577":[{"snaktype":"value","property":"P577","hash":"fde79ecb015112d2f29229ccc1ec514ed3e71fa2","datavalue":{"value":{"time":"+2013-10-28T00:00:00Z","timezone":0,"before":0,"after":0,"precision":11,"calendarmodel":"http://www.wikidata.org/entity/Q1985727"},"type":"time"},"datatype":"time"}\]},"snaks-order":\["P248","P577"\]}\]}\],"P1482":\[{"mainsnak":{"snaktype":"value","property":"P1482","hash":"d55f4d13fad5f2e147e168b7637b4391d9fa2e3f","datavalue":{"value":"https://stackoverflow.com/tags/verilog","type":"string"},"datatype":"url"},"type":"statement","id":"Q827773$D4CA6206-DF70-41B5-886C-93A47B484757","rank":"normal"}\],"P737":\[{"mainsnak":{"snaktype":"value","property":"P737","hash":"8ff48439cf3b7d174ea96e99fdc7fb9692f31a76","datavalue":{"value":{"entity-type":"item","numeric-id":15777,"id":"Q15777"},"type":"wikibase-entityid"},"datatype":"wikibase-item"},"type":"statement","id":"Q827773$2A5FBF6D-13DF-4122-B83C-A4D9D687C5D2","rank":"normal"},{"mainsnak":{"snaktype":"value","property":"P737","hash":"07269858ebfb05892af7f8289c2a5983f2576478","datavalue":{"value":{"entity-type":"item","numeric-id":81571,"id":"Q81571"},"type":"wikibase-entityid"},"datatype":"wikibase-item"},"type":"statement","id":"Q827773$db1ce6e0-4528-d65f-2d39-a6a74c0ea0ac","rank":"normal","references":\[{"hash":"2f2001d5a631f9d76370f9a388c0ed92eb2213fb","snaks":{"P854":\[{"snaktype":"value","property":"P854","hash":"b29892d411fad1af2302a9155f305a07bc1f0f06","datavalue":{"value":"https://www.physi.uni-heidelberg.de/\~angelov/VHDL/VHDL\_SS09\_Teil10.pdf","type":"string"},"datatype":"url"}\]},"snaks-order":\["P854"\]},{"hash":"aff41d89b6a32d92e26ba039bc5b0ae5af019c2f","snaks":{"P212":\[{"snaktype":"value","property":"P212","hash":"d0a396187493f7d2b735cbc91d3478f854ca767a","datavalue":{"value":"9783486711509","type":"string"},"datatype":"external-id"}\]},"snaks-order":\["P212"\]}\]},{"mainsnak":{"snaktype":"value","property":"P737","hash":"3217879189187d624c2084dc94c35244411369a2","datavalue":{"value":{"entity-type":"item","numeric-id":154755,"id":"Q154755"},"type":"wikibase-entityid"},"datatype":"wikibase-item"},"type":"statement","id":"Q827773$d499ab48-4c59-98e4-446e-9fc27aadebb6","rank":"normal","references":\[{"hash":"2f2001d5a631f9d76370f9a388c0ed92eb2213fb","snaks":{"P854":\[{"snaktype":"value","property":"P854","hash":"b29892d411fad1af2302a9155f305a07bc1f0f06","datavalue":{"value":"https://www.physi.uni-heidelberg.de/\~angelov/VHDL/VHDL\_SS09\_Teil10.pdf","type":"string"},"datatype":"url"}\]},"snaks-order":\["P854"\]}\]}\],"P3417":\[{"mainsnak":{"snaktype":"value","property":"P3417","hash":"e098f95cf374bb32a5603a0ba2dc26174755fedf","datavalue":{"value":"Verilog","type":"string"},"datatype":"external-id"},"type":"statement","id":"Q827773$B6FA222A-74B0-4C53-B8BF-B1D81725EF89","rank":"normal","references":\[{"hash":"3b0a5bb3c1f955edce73740124f7d935698092ad","snaks":{"P248":\[{"snaktype":"value","property":"P248","hash":"3ac9682e789a3a3791d4fd088b265ea03abef101","datavalue":{"value":{"entity-type":"item","numeric-id":51711,"id":"Q51711"},"type":"wikibase-entityid"},"datatype":"wikibase-item"}\]},"snaks-order":\["P248"\]}\]}\],"P571":\[{"mainsnak":{"snaktype":"value","property":"P571","hash":"f9ad83e5dbc573ccbb6abc602e301da90d23744f","datavalue":{"value":{"time":"+1984-01-01T00:00:00Z","timezone":0,"before":0,"after":0,"precision":9,"calendarmodel":"http://www.wikidata.org/entity/Q1985727"},"type":"time"},"datatype":"time"},"type":"statement","id":"Q827773$FC3379ED-6E5F-4666-918F-AFFE2E48E52D","rank":"normal","references":\[{"hash":"fa278ebfc458360e5aed63d5058cca83c46134f1","snaks":{"P143":\[{"snaktype":"value","property":"P143","hash":"e4f6d9441d0600513c4533c672b5ab472dc73694","datavalue":{"value":{"entity-type":"item","numeric-id":328,"id":"Q328"},"type":"wikibase-entityid"},"datatype":"wikibase-item"}\]},"snaks-order":\["P143"\]}\]}\],"P1195":\[{"mainsnak":{"snaktype":"value","property":"P1195","hash":"bf9f586deae8b3ee01a3870ab89ba38f35f2273a","datavalue":{"value":"v","type":"string"},"datatype":"string"},"type":"statement","id":"Q827773$A8F10614-C88D-440A-99D7-8C746FC8A095","rank":"normal","references":\[{"hash":"fa278ebfc458360e5aed63d5058cca83c46134f1","snaks":{"P143":\[{"snaktype":"value","property":"P143","hash":"e4f6d9441d0600513c4533c672b5ab472dc73694","datavalue":{"value":{"entity-type":"item","numeric-id":328,"id":"Q328"},"type":"wikibase-entityid"},"datatype":"wikibase-item"}\]},"snaks-order":\["P143"\]}\]}\],"P3966":\[{"mainsnak":{"snaktype":"value","property":"P3966","hash":"8587701cac9cb144fd209df92fd50a767482fb38","datavalue":{"value":{"entity-type":"item","numeric-id":223335,"id":"Q223335"},"type":"wikibase-entityid"},"datatype":"wikibase-item"},"type":"statement","id":"Q827773$FE509B38-4409-46FB-BA50-3E907A4B4649","rank":"normal","references":\[{"hash":"fa278ebfc458360e5aed63d5058cca83c46134f1","snaks":{"P143":\[{"snaktype":"value","property":"P143","hash":"e4f6d9441d0600513c4533c672b5ab472dc73694","datavalue":{"value":{"entity-type":"item","numeric-id":328,"id":"Q328"},"type":"wikibase-entityid"},"datatype":"wikibase-item"}\]},"snaks-order":\["P143"\]}\]}\],"P244":\[{"mainsnak":{"snaktype":"value","property":"P244","hash":"30df7141648194641c8dbf7edb8f2ececc5d0fc6","datavalue":{"value":"sh90004761","type":"string"},"datatype":"external-id"},"type":"statement","id":"Q827773$D7400134-4F09-4C88-A06E-096284DD0FBE","rank":"normal","references":\[{"hash":"ac5d47e9fbcc281bc0d27a205ae02e22ad24ce31","snaks":{"P854":\[{"snaktype":"value","property":"P854","hash":"b560dc6b281a39d061e189d2eb299a426a06f1a2","datavalue":{"value":"https://github.com/JohnMarkOckerbloom/ftl/blob/master/data/wikimap","type":"string"},"datatype":"url"}\],"P813":\[{"snaktype":"value","property":"P813","hash":"0dcf4f64e93fdcc654e2c7534285881fe48b9f3d","datavalue":{"value":{"time":"+2019-04-03T00:00:00Z","timezone":0,"before":0,"after":0,"precision":11,"calendarmodel":"http://www.wikidata.org/entity/Q1985727"},"type":"time"},"datatype":"time"}\]},"snaks-order":\["P854","P813"\]}\]}\],"P6366":\[{"mainsnak":{"snaktype":"value","property":"P6366","hash":"e8f532f525689e06fef2e90d8231dfdfd0a1f54b","datavalue":{"value":"2779030575","type":"string"},"datatype":"external-id"},"type":"statement","id":"Q827773$218F6144-820E-46AE-9193-1BFC3A4601D8","rank":"normal"}\],"P1889":\[{"mainsnak":{"snaktype":"value","property":"P1889","hash":"2815ca87bee8cc98670a79367a4ca09ca0d2c202","datavalue":{"value":{"entity-type":"item","numeric-id":674926,"id":"Q674926"},"type":"wikibase-entityid"},"datatype":"wikibase-item"},"type":"statement","id":"Q827773$667FDFAB-40DC-46C5-A69B-3FA94F97CE7D","rank":"normal","references":\[{"hash":"d36e1965627ef068ffca88df57c2b50d93a72283","snaks":{"P143":\[{"snaktype":"value","property":"P143","hash":"e4f6d9441d0600513c4533c672b5ab472dc73694","datavalue":{"value":{"entity-type":"item","numeric-id":328,"id":"Q328"},"type":"wikibase-entityid"},"datatype":"wikibase-item"}\],"P4656":\[{"snaktype":"value","property":"P4656","hash":"b5b4cd4826e03da37181e60e2b3f08d42899638b","datavalue":{"value":"https://en.wikipedia.org/w/index.php?title=Verilog&oldid=949765139","type":"string"},"datatype":"url"}\]},"snaks-order":\["P143","P4656"\]}\]}\],"P7078":\[{"mainsnak":{"snaktype":"value","property":"P7078","hash":"702fd94d4cd46b5288a2e907ba954c587a44ffd1","datavalue":{"value":{"entity-type":"item","numeric-id":7977969,"id":"Q7977969"},"type":"wikibase-entityid"},"datatype":"wikibase-item"},"type":"statement","id":"Q827773$10179E24-C773-444D-BF42-51A404F7C143","rank":"normal","references":\[{"hash":"f63670b6394f592a4592816faa01b118c516e556","snaks":{"P143":\[{"snaktype":"value","property":"P143","hash":"e4f6d9441d0600513c4533c672b5ab472dc73694","datavalue":{"value":{"entity-type":"item","numeric-id":328,"id":"Q328"},"type":"wikibase-entityid"},"datatype":"wikibase-item"}\],"P4656":\[{"snaktype":"value","property":"P4656","hash":"d1580f5d34ed5e8f8e3450682a5ec1a36a1b69e3","datavalue":{"value":"https://en.wikipedia.org/w/index.php?title=Verilog&oldid=995607887","type":"string"},"datatype":"url"}\]},"snaks-order":\["P143","P4656"\]}\]},{"mainsnak":{"snaktype":"value","property":"P7078","hash":"2a025b6111b890172123211cd768b891c361ef48","datavalue":{"value":{"entity-type":"item","numeric-id":1940914,"id":"Q1940914"},"type":"wikibase-entityid"},"datatype":"wikibase-item"},"type":"statement","id":"Q827773$ab84d23f-4b7e-853e-5934-77ecd3ecc395","rank":"normal"}\],"P3553":\[{"mainsnak":{"snaktype":"value","property":"P3553","hash":"3fc369e1ccfabcb0f4c71ae6d0368b4c70dcfb13","datavalue":{"value":"19609390","type":"string"},"datatype":"external-id"},"type":"statement","id":"Q827773$E7B061B8-1E1F-4B1A-AE2D-C2FD415E1C7F","rank":"normal"}\],"P8189":\[{"mainsnak":{"snaktype":"value","property":"P8189","hash":"730c6185da761cdeb218609b8faf8c86a98b0c29","datavalue":{"value":"987007536924105171","type":"string"},"datatype":"external-id"},"type":"statement","id":"Q827773$330C7200-56EF-4DE2-AF65-9788FB8E4EBC","rank":"normal","references":\[{"hash":"c8a47202c92936005b390eb36ddd267921b51f43","snaks":{"P248":\[{"snaktype":"value","property":"P248","hash":"0ea73b3596b49258a7b7ec6495950779b99e875d","datavalue":{"value":{"entity-type":"item","numeric-id":188915,"id":"Q188915"},"type":"wikibase-entityid"},"datatype":"wikibase-item"}\]},"snaks-order":\["P248"\]}\]}\],"P10283":\[{"mainsnak":{"snaktype":"value","property":"P10283","hash":"d69fde31302e94e73809c969ff85c36c3902697a","datavalue":{"value":"C2779030575","type":"string"},"datatype":"external-id"},"type":"statement","id":"Q827773$54DF58D7-00A9-44C3-B0DB-41C5D29C5731","rank":"normal","references":\[{"hash":"c13ba4d7902ead2693f79396bc25bd35d4d14030","snaks":{"P248":\[{"snaktype":"value","property":"P248","hash":"4a4f26a5361b5707266e48e425bf2be2f99fd2ab","datavalue":{"value":{"entity-type":"item","numeric-id":107507571,"id":"Q107507571"},"type":"wikibase-entityid"},"datatype":"wikibase-item"}\],"P813":\[{"snaktype":"value","property":"P813","hash":"435834d08182bb9f3dbe974ba9840af0f12899cc","datavalue":{"value":{"time":"+2022-01-26T00:00:00Z","timezone":0,"before":0,"after":0,"precision":11,"calendarmodel":"http://www.wikidata.org/entity/Q1985727"},"type":"time"},"datatype":"time"}\],"P854":\[{"snaktype":"value","property":"P854","hash":"a4a4bf53f22268815c51ec10fed608da703c9c7f","datavalue":{"value":"https://docs.openalex.org/download-snapshot/snapshot-data-format","type":"string"},"datatype":"url"}\]},"snaks-order":\["P248","P813","P854"\]}\]}\],"P691":\[{"mainsnak":{"snaktype":"value","property":"P691","hash":"38de667b65f7b79a6080617530df4acc23c7e800","datavalue":{"value":"ph756338","type":"string"},"datatype":"external-id"},"type":"statement","qualifiers":{"P1810":\[{"snaktype":"value","property":"P1810","hash":"58f8f592eb428dc9782a1627924acd1142542ee7","datavalue":{"value":"Verilog (programovac\u00ed jazyk)","type":"string"},"datatype":"string"}]},"qualifiers-order":["P1810"],"id":"Q827773$5C845713-62D1-46CC-9A14-40007E266F70","rank":"normal"}],"P348":[{"mainsnak":{"snaktype":"value","property":"P348","hash":"3d4adbb7f8734321c2f6f0508fc3870325ba92a8","datavalue":{"value":"IEEE 1364-2005","type":"string"},"datatype":"string"},"type":"statement","qualifiers":{"P577":[{"snaktype":"value","property":"P577","hash":"ee3ab2963a4630a826bdec4696c16eb6dd5d51f8","datavalue":{"value":{"time":"+2006-04-07T00:00:00Z","timezone":0,"before":0,"after":0,"precision":11,"calendarmodel":"http://www.wikidata.org/entity/Q1985727"},"type":"time"},"datatype":"time"}\]},"qualifiers-order":\["P577"\],"id":"Q827773$27572a64-4669-7b25-62f1-f905887a8c5d","rank":"normal","references":\[{"hash":"982760bdcbe3ce8b3e8182efc3befc4a27ab3708","snaks":{"P854":\[{"snaktype":"value","property":"P854","hash":"6fa7dc4cf06ffddc3f799edc467fac764f2fcccc","datavalue":{"value":"https://ieeexplore.ieee.org/document/1620780","type":"string"},"datatype":"url"}\]},"snaks-order":\["P854"\]}\]},{"mainsnak":{"snaktype":"value","property":"P348","hash":"dd0ff2ea0cf83d84f824ee4764683d93b3ae754d","datavalue":{"value":"IEEE 1800-2023","type":"string"},"datatype":"string"},"type":"statement","id":"Q827773$9b7c1475-4917-d66b-1af4-6a476faf9ced","rank":"preferred","references":[{"hash":"688d76c78dab395dad405eb9ea267ea2005c3b9a","snaks":{"P854":[{"snaktype":"value","property":"P854","hash":"80018f5ace5bf89b8dc392bb044811b564a2d6c6","datavalue":{"value":"https://ieeexplore.ieee.org/document/10458102","type":"string"},"datatype":"url"}\]},"snaks-order":\["P854"\]}\]}\],"P227":\[{"mainsnak":{"snaktype":"value","property":"P227","hash":"0f2c44d0d07e03e434ad472e36dddfd7a3248521","datavalue":{"value":"4268385-3","type":"string"},"datatype":"external-id"},"type":"statement","qualifiers":{"P1810":\[{"snaktype":"value","property":"P1810","hash":"d1f144aaec8c91563ac503bde60933f8ffcab30e","datavalue":{"value":"VERILOG","type":"string"},"datatype":"string"}\]},"qualifiers-order":\["P1810"\],"id":"Q827773$64987d1e-43c2-b4ec-1143-74e4ccc997e5","rank":"normal"}\],"P12946":\[{"mainsnak":{"snaktype":"value","property":"P12946","hash":"3fe6680528547dff3fa2b77d35e5c908615d6601","datavalue":{"value":"Verilog","type":"string"},"datatype":"external-id"},"type":"statement","id":"Q827773$FCB0F23B-4045-493B-8439-4627F5AC9B5E","rank":"normal"}\],"P8885":\[{"mainsnak":{"snaktype":"value","property":"P8885","hash":"e76e3a44bbcb7582b59792e4d20b2f0867a861c9","datavalue":{"value":"\\ubca0\\ub9b4\\ub85c\\uadf8","type":"string"},"datatype":"external-id"},"type":"statement","id":"Q827773$75d54ee0-46fd-a227-df2c-2dbc865de924","rank":"normal"}\]},"sitelinks":{"arwiki":{"site":"arwiki","title":"\\u0641\\u064a\\u0631\\u064a\\u0644\\u0648\\u062c (\u0628\u0631\u0645\u062c\u0629)","badges":[],"url":"https://ar.wikipedia.org/wiki/%D9%81%D9%8A%D8%B1%D9%8A%D9%84%D9%88%D8%AC\_(%D8%A8%D8%B1%D9%85%D8%AC%D8%A9)"},"cawiki":{"site":"cawiki","title":"Verilog","badges":\[\],"url":"https://ca.wikipedia.org/wiki/Verilog"},"cswiki":{"site":"cswiki","title":"Verilog","badges":\[\],"url":"https://cs.wikipedia.org/wiki/Verilog"},"dewiki":{"site":"dewiki","title":"Verilog","badges":\[\],"url":"https://de.wikipedia.org/wiki/Verilog"},"enwiki":{"site":"enwiki","title":"Verilog","badges":\[\],"url":"https://en.wikipedia.org/wiki/Verilog"},"enwikiversity":{"site":"enwikiversity","title":"Verilog","badges":\[\],"url":"https://en.wikiversity.org/wiki/Verilog"},"eswiki":{"site":"eswiki","title":"Verilog","badges":\[\],"url":"https://es.wikipedia.org/wiki/Verilog"},"etwiki":{"site":"etwiki","title":"Verilog","badges":\[\],"url":"https://et.wikipedia.org/wiki/Verilog"},"fawiki":{"site":"fawiki","title":"\\u0648\\u0631\\u06cc\\u0644\\u0627\\u06af","badges":\[\],"url":"https://fa.wikipedia.org/wiki/%D9%88%D8%B1%DB%8C%D9%84%D8%A7%DA%AF"},"frwiki":{"site":"frwiki","title":"Verilog","badges":\[\],"url":"https://fr.wikipedia.org/wiki/Verilog"},"hewiki":{"site":"hewiki","title":"Verilog","badges":\[\],"url":"https://he.wikipedia.org/wiki/Verilog"},"huwiki":{"site":"huwiki","title":"Verilog","badges":\[\],"url":"https://hu.wikipedia.org/wiki/Verilog"},"hywiki":{"site":"hywiki","title":"\\u054e\\u0565\\u0580\\u056b\\u056c\\u0578\\u0563","badges":\[\],"url":"https://hy.wikipedia.org/wiki/%D5%8E%D5%A5%D6%80%D5%AB%D5%AC%D5%B8%D5%A3"},"iswiki":{"site":"iswiki","title":"Verilog","badges":\[\],"url":"https://is.wikipedia.org/wiki/Verilog"},"itwiki":{"site":"itwiki","title":"Verilog","badges":\[\],"url":"https://it.wikipedia.org/wiki/Verilog"},"jawiki":{"site":"jawiki","title":"Verilog","badges":\[\],"url":"https://ja.wikipedia.org/wiki/Verilog"},"kowiki":{"site":"kowiki","title":"\\ubca0\\ub9b4\\ub85c\\uadf8","badges":\[\],"url":"https://ko.wikipedia.org/wiki/%EB%B2%A0%EB%A6%B4%EB%A1%9C%EA%B7%B8"},"nlwiki":{"site":"nlwiki","title":"Verilog","badges":\[\],"url":"https://nl.wikipedia.org/wiki/Verilog"},"nowiki":{"site":"nowiki","title":"Verilog","badges":\[\],"url":"https://no.wikipedia.org/wiki/Verilog"},"plwiki":{"site":"plwiki","title":"Verilog","badges":\[\],"url":"https://pl.wikipedia.org/wiki/Verilog"},"ptwiki":{"site":"ptwiki","title":"Verilog","badges":\[\],"url":"https://pt.wikipedia.org/wiki/Verilog"},"rowiki":{"site":"rowiki","title":"Verilog","badges":\[\],"url":"https://ro.wikipedia.org/wiki/Verilog"},"ruwiki":{"site":"ruwiki","title":"Verilog","badges":\[\],"url":"https://ru.wikipedia.org/wiki/Verilog"},"srwiki":{"site":"srwiki","title":"\\u0412\\u0435\\u0440\\u0438\\u043b\\u043e\\u0433","badges":\[\],"url":"https://sr.wikipedia.org/wiki/%D0%92%D0%B5%D1%80%D0%B8%D0%BB%D0%BE%D0%B3"},"svwiki":{"site":"svwiki","title":"Verilog","badges":\[\],"url":"https://sv.wikipedia.org/wiki/Verilog"},"trwiki":{"site":"trwiki","title":"Verilog","badges":\[\],"url":"https://tr.wikipedia.org/wiki/Verilog"},"ukwiki":{"site":"ukwiki","title":"Verilog","badges":\[\],"url":"https://uk.wikipedia.org/wiki/Verilog"},"viwiki":{"site":"viwiki","title":"Verilog","badges":\[\],"url":"https://vi.wikipedia.org/wiki/Verilog"},"wuuwiki":{"site":"wuuwiki","title":"Verilog","badges":\[\],"url":"https://wuu.wikipedia.org/wiki/Verilog"},"zhwiki":{"site":"zhwiki","title":"Verilog","badges":\["Q17437798"\],"url":"https://zh.wikipedia.org/wiki/Verilog"}}}}}