[LLVMdev] Some questions on SelectionDAG (original) (raw)

Zakk zakk0610 at gmail.com
Fri Sep 2 03:14:37 PDT 2011

• Previous message: [LLVMdev] Best way to use LLVM with byte code vm
• Next message: [LLVMdev] Some questions on SelectionDAG
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

Hi, all

I am studying the ARM backend on SelectionDAG, I have some following questions:

1. Each operator of SDNode in SelectionDAG is required to be defined by SDNodeISD::XXX,XXX,XXX in .td file, right?

But several operators are not defined in .td file, why? (e.g., ISD::BR_CC, ISD::CopyToReg, ISD::AssertSext)

1. The MVT::glue value is used to ensure two nodes are scheduled together and in order.

In the other word, we can’t insert any instruction of them in the scheduling, is it correct?

1. In the ARMISelLowering constructor, it sets the callback function with

setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);

My question is ARM don’t support MVT::i1 registerclass, why should it determine this operation with MVT::i1 value?

Can anyone tell me?

Thank you very much.

Best regards,

Zakk -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110902/886c3b23/attachment.html>

• Previous message: [LLVMdev] Best way to use LLVM with byte code vm
• Next message: [LLVMdev] Some questions on SelectionDAG
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-dev mailing list