[LLVMdev] bug in tablegen? (original) (raw)
Sean Silva silvas at purdue.edu
Mon Jul 2 21:26:51 PDT 2012
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I think you're missing the template args for FRRR16_ins in the first
argument. The switch in TGParser::ParseType() doesn't cover the case
of types with template args though... which makes me wonder what is
going on inside of TableGen to make I.f and I.AsmString valid...
--Sean Silva
On Mon, Jul 2, 2012 at 8:07 PM, reed kotler <rkotler at mips.com> wrote:
I've filed the following bug. Maybe I'm doing something stupid here or maybe someone knows of a workaround.
The following fragment from mips16 (not yet checked into main source). The problem is that I should be able to pass parameters: I.OutOperandList, I.InOperandList But instead, I must back substitute what I know the values of these are. (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz)
class FRRR16ins<bits<2> f, string asmstr, list pattern, InstrItinClass itin> : FRRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx,_ _CPU16Regs:$ry),_ _!strconcat(asmstr, "\t$rz, rx,rx, rx,ry"), pattern, itin>; class ArithLogicR16<FRRR16ins I, SDNode OpNode, bit isComm = 0>: FRRR16<I.f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz),_ _// tablegen bug: should be I.OutOperandList, I.InOperandList,_ _I.AsmString,_ _[(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))],_ _I.Itinerary > { let isCommutable = isComm; let isReMaterializable = 1; }
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