[LLVMdev] Purpose of MSP430Wrapper (original) (raw)

Richard Osborne richard at xmos.com
Wed Jul 25 09:26:21 PDT 2012


On 25/07/12 12:14, Paul Shortis wrote:

Thanks Richard,

You're correct, they are similar. In the XCoreInstrInfo.td patterns what I'm struggling with is why this .... def BLlu10 : FLU10<_ _(outs),_ _(ins calltarget:$target, variableops),_ _"bl $target",_ _[(XCoreBranchLink immU20:$target)]>; def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BLlu10_ _tglobaladdr:$addr)>; def : Pat<(XCoreBranchLink texternalsym:$addr), (BLlu10_ _texternalsym:$addr)>; is necessary. Are the Pat<> s just 'casting' tglobaladdr:$addr and texternalsym:$addr to an immU20 to force a match ? There is no casting going on, there are just 3 separate patterns all which select to the BL_lu10 instruction. You could rewrite this as:

def BL_lu10 : _FLU10< (outs), (ins calltarget:$target, variable_ops), "bl $target", []>;

def : Pat<(XCoreBranchLink immU20:$addr), (BL_lu10 immU20:$addr)>; def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>; def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>;

The advantage of specifying the pattern inline is:

I'm guessing similar Pat<> 's aren't required for the BLu10/immU10 cases because they match without any assistance ? No, the BL_u10 instructions are not matched. At least for the XCore target, we always conservatively use the branch instruction with the largest offset. instructions can be relaxed (replaced by smaller versions) later. Is the XCoreBranchLink enough of a match hint that an address wrapper isn't required to clarify the pattern match for these call instructions? There's no wrapper in these patterns because the lowering code which creates the XCoreBranchLink SDNode (XCoreTargetLowering::LowerCCCCallTo()) doesn't add a wrapper around the callee. There is no need to add a wrapper because in the case of a call there is no ambiguity - a call of a global always use pc relative addressing on the XCore. The important thing here is that the pattern must match the nodes the introduced during the lowering. Cheers, Paul

-- Richard Osborne | XMOS http://www.xmos.com



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