[LLVMdev] Adding masked vector load and store intrinsics (original) (raw)
dag at cray.com dag at cray.com
Fri Oct 24 13:02:54 PDT 2014
- Previous message: [LLVMdev] Adding masked vector load and store intrinsics
- Next message: [LLVMdev] Adding masked vector load and store intrinsics
- Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]
Nadav Rotem <nrotem at apple.com> writes:
I oppose adding new first-level instructions because we would need to teach all of the existing optimizations about the new instructions, and considering the limited usefulness of masked operations it is not worth the effort.
Limited usefulness? It is quite the opposite. If we were starting from scratch on an IR, we'd want to have first-class mask support, with masks as an additional operand to nearly every IR instructions. Given where we are, target-independent intrinsics seems like a good compromise because as you said it would be a huge task to teach all of the existing LLVM code about a new instruction operand. With intrinsics, passes are conservative when they see an intrinsic they don't understand. We can teach passes about specific intrinsics as we find benefit in doing so.
-David
- Previous message: [LLVMdev] Adding masked vector load and store intrinsics
- Next message: [LLVMdev] Adding masked vector load and store intrinsics
- Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]