[llvm-dev] RFC: Implement variable-sized register classes (original) (raw)

Alex Bradbury via llvm-dev llvm-dev at lists.llvm.org
Sun Oct 9 05:38:51 PDT 2016

On 8 October 2016 at 20:52, Alex Bradbury <asb at asbradbury.org> wrote:

A closely related to variable-sized register classes is the case where you have multiple registers with the same AsmName. This crops up in the same kind of cases where you have multiple instructions with the same encoding. Without a workaround, an assert is tripped in llvm-tblgen when trying to produce a StringSwitch for MatchRegisterName. The solution in Mips, PPC and others seems to be involve the generation of MatchRegisterName. What has been discussed so far with regards to HwMode and variable-size register classes points to a solution, but I don't think it's quite enough. Options include:

1. Only have one set of register definitions, and have the variable sized register class determine the bit width. The problem is there are often some instructions where I think you need to have registers modelled as subregisters. e.g. SLLW, ADDW etc in 64-bit RISC-V. These operate on 32-bit values and write the results sign-extended to the target 64-bit register. 2. Define both the 64-bit registers and the 32-bit subregisters, but make MatchRegisterName's behaviour change based on the HwMode. This works around the fact there are multiple registers with the same AsmName. Although I doubt this would actually cause problems, this still isn't quite right. For an SLLIW x1, x2, 5 I think the correct interpretation would have x1 as a 64-bit target register and x2 as the 32-bit subregister that happens to have the same AsmName as the 64-bit x2 register. Have you thought about how the HwMode/variable-sized register class proposal might interact with register AsmNames at all?

I've thought about this some more. In a future world supporting variable-sized register classes, you'd define one main set of registers with AltNames and and AsmName. The auto-generated MatchRegisterName and MatchRegisterAltName can be used for these. You might define 32-bit subregisters as well as an associated GPR32 reg class for use in instructions that need it, but these have no AltNames or AsmName. The AsmParser can convert parsed register numbers when desired (e.g. for SLLIW).

In my case, I would define Xnn_XLEN registers for RISC-V. These are included in the 'GPR' variable-sized register class which makes use of HwMode. I would also need to define these as having Xnn_32 subregisters and define a GPR32 regclass. I think something similar could be done for MIPS.

Apologies for thinking out loud, I'm just trying to work through how everything would fit together should we go with this approach.

Alex

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