[llvm-dev] Generate Register Indirect mode instruction (original) (raw)

Alex Bradley via llvm-dev llvm-dev at lists.llvm.org
Wed Oct 12 13:54:17 PDT 2016

Hi Ryan,

Do you mean something like this -

@a = local_unnamed_addr global i32 0, align 4 @b = local_unnamed_addr global i32 0, align 4 @c = local_unnamed_addr global i32 0, align 4

; Function Attrs: norecurse nounwind define void @foo() { entry: %add = add nsw i32 @a, @b

store i32 %add, i32* @c, align 4 ret void }

If yes, should this be done at IR level or SelectionDAG? Any side effect of doing it at IR level?

But above seems memory to memory without involving registers to point to memory locations, which doesn't match the addressing mode of my target.

Thanks.

Regards, Alex

On 12 Oct 2016 11:09 p.m., "Ryan Taylor" <ryta1203 at gmail.com> wrote:

Could you eliminate the load in the DAG and propagate the address to the add? Have you tried this, I'm curious. Then in table gen, just match the add appropriately. -Ryan On Mon, Oct 10, 2016 at 12:01 PM, Alex Bradley <alexbradley.bqc at gmail.com> wrote:

Hi Ryan, Somewhat yes. But the memory locations should be pointed by registers. Essentially, load the address of memory location onto the registers and then use them to point to memory location. Regards, Alex

On 10 Oct 2016 8:52 p.m., "Ryan Taylor" <ryta1203 at gmail.com> wrote: Alex, So, you are trying to do direct mem to mem add? Like: ADD A, B, C -Ryan _On Mon, Oct 10, 2016 at 10:23 AM, Alex Bradley via llvm-dev <_ llvm-dev at lists.llvm.org> wrote:

Hi All, I am new to llvm backend. I am trying out few examples to understand backend codegen. I have ported llvm LEG @ https://github.com/frasercrmck/llvm-leg to llvm 3.9 successfully. Currently, the LEG instructions are RISC load-store type instruction. I want to generate some instructions for register indirect mode, like following: IR: @a = localunnamedaddr global i32 0, align 4 @b = localunnamedaddr global i32 0, align 4 @c = localunnamedaddr global i32 0, align 4 ; Function Attrs: norecurse nounwind define void @foo() { entry: %0 = load i32, i32* @a, align 4 %1 = load i32, i32* @b, align 4 %add = add nsw i32 %1, %0 store i32 %add, i32* @c, align 4 ret void }

Expected assembly instructions: MOV R0, #A // R0 pointing to address of A MOV R1, #B // R1 pointing to address of B ADD *R0, *R1 // Adding both memory operands MOV #C, *R0 // Moving result to address of C How should i define such mov and add instruction in my .td files? How will ISD::LOAD be seleted in ISelDAGtoDAG in select() function? I want to start with simple .td definitions and would later like to encapsulate them in multiclass once basic example works. Can someone please help how to achieve this? Regards, Alex

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