[llvm-dev] mischeduler (original) (raw)
Jonas Paulsson via llvm-dev llvm-dev at lists.llvm.org
Fri Oct 28 03:04:18 PDT 2016
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Hi,
Regarding the mischeduler, I wonder
// For loops that are acyclic path limited, aggressively schedule for // latency. This can result in very long dependence chains scheduled in // sequence, so once every cycle (when CurrMOps == 0), switch to normal // heuristics. if (Rem.IsAcyclicLatencyLimited && !Zone->getCurrMOps() && tryLatency(TryCand, Cand, *Zone)) return;
Is this an error in comment or code? The CurrMOps is 0 once per cycle, which means this is actually done once per cycle, in contrast to what the comment suggests.
...
// Schedule aggressively for latency in PostRA mode. We don't check for // acyclic latency during PostRA, and highly out-of-order processors will // skip PostRA scheduling. if (!OtherResLimited) { if (IsPostRA || (RemLatency + CurrZone.getCurrCycle() > Rem.CriticalPath)) { Policy.ReduceLatency |= true;
Why !OtherResLimited? tryCandidate() has already checked for resource balancing just before this. To not do the latency check then only means falling back to original order.
/Jonas
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