[llvm-dev] Question about quad-register (original) (raw)

陳韋任 via llvm-dev llvm-dev at lists.llvm.org
Sun Sep 10 15:40:35 PDT 2017

Hi Anton,

I guess you mean something like this in RegisterInfo.td?

def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64,

v2f32, v4f16], 64, (sequence "D%u", 0, 31)> {

def Tuples2DSpc : RegisterTuples<[dsub_0, dsub_2],
                                                        [(shl DPR, 0),
                                                         (shl DPR, 2)]>;

or this?

let SubRegIndices = [dsub_0, dsub_1] in { def Q0 : ARMReg< 0, "q0", [D0, D1]>; def Q1 : ARMReg< 1, "q1", [D2, D3]>; }

Regards, chenwj

2017-09-11 3:07 GMT+08:00 Anton Korobeynikov <anton at korobeynikov.info>:

The standard trick is to define the "quad register" that would alias r0/r1/r2/r3. See e.g. ARM backend.

On Sun, Sep 10, 2017 at 6:17 AM, 陳韋任 via llvm-dev <llvm-dev at lists.llvm.org> wrote: Hi All,

If the target supports quad-register R0:R1:R2:R3 (Rn is 32-bit register), is it possible mapping quad-register to v4i32 so that the following example work? typedef int v4si attribute ((vectorsize (16))); void foo(v4si i) { v4si j = i; } I don't know how to write CallingConv.td to represent the concept of occupying quad-register R0:R1:R2:R3 once seeing v4i32. Any example that I can refer to? Thanks. Regards, chenwj -- Wei-Ren Chen (陳韋任) Homepage: https://people.cs.nctu.edu.tw/~chenwj

LLVM Developers mailing list llvm-dev at lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev

-- With best regards, Anton Korobeynikov Department of Statistical Modelling, Saint Petersburg State University

-- Wei-Ren Chen (陳韋任) Homepage: https://people.cs.nctu.edu.tw/~chenwj

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