[llvm-dev] VSelect Instruction Error (original) (raw)

Nemanja Ivanovic via llvm-dev llvm-dev at lists.llvm.org
Thu Sep 21 01:26:15 PDT 2017

Well, the message mentions it. It's the vselect node in the .td file (ISD::VSELECT). You've clearly legalized it or otherwise emitted it post-legalization. So you need something similar to this in your .td file (but for your big vector type):

let Predicates = [HasAVX2] in {
  def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
                            (v32i8 VR256:$src2))),
            (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
}

This particular example comes from lib/Target/X86/X86InstrSSE.td, but there are other examples from other back ends that may be more fitting.

On Thu, Sep 21, 2017 at 10:18 AM, hameeza ahmed via llvm-dev < llvm-dev at lists.llvm.org> wrote:

Hello,

I am getting this error. What instruction is required to be implemented?

LLVM ERROR: Cannot select: t22: v32i32 = vselect t724, t11, t16 t724: v32i32,ch = load<LD128[FixedStack1]> t723, FrameIndex:i64<1>, undef:i64 t659: i64 = FrameIndex<1> t10: i64 = undef t11: v32i32,ch = load<LD128%sunkaddr45(tbaa=<0x481f1e8>)> t0, t8, undef:i64 t8: i64 = add t7, Constant:i64<4> t7: i64 = add t2, t63 t2: i64,ch = CopyFromReg t0, Register:i64 %vreg97 t1: i64 = Register %vreg97 t63: i64 = shl t4, Constant:i8<2> t4: i64,ch = CopyFromReg t0, Register:i64 %vreg11 t3: i64 = Register %vreg11 t1889: i8 = Constant<2> t5: i64 = Constant<4> t10: i64 = undef t16: v32i32,ch = CopyFromReg t0, Register:v32i32 %vreg14 t15: v32i32 = Register %vreg14 In function: inttouchar

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