[llvm-dev] MC Assembler / tablegen: actually parsing variable_ops (original) (raw)

Friedman, Eli via llvm-dev llvm-dev at lists.llvm.org
Mon Dec 3 17:51:42 PST 2018

On 12/3/2018 5:32 PM, Wouter van Oortmerssen via llvm-dev wrote:

variableops is used in the tablegen defs for many targets to denote instructions that a variable number of inputs, but it seems that there aren't any targets for which this results in variable elements in the instruction encoding (and thus in assembler parsing), since the tablegen generated assembly matcher ($(Target)GenAsmMatcher.inc) simply assumes that variableops are not to be parsed (match table: ConvertNoOperands).

ARM has ldm/stm, which take a variable number of register operands.  You might want to look at how ARMInstrInfo.td uses a "reglist" operand to represent the list of registers.

-Eli

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