[llvm-dev] Branch relaxation at assembler level (RISCV) (original) (raw)

Friedman, Eli via llvm-dev llvm-dev at lists.llvm.org
Wed Dec 5 13:48:58 PST 2018

On 12/5/2018 1:05 PM, Stefan Pintilie wrote:

Hi,

This discussion caught my eye because we are also looking at a very similar problem on PowerPC. We have a situation where we want to align a given instruction to a 64 byte boundary. If it's not already aligned we just add nops until it is aligned (We plan to do this in a custom PPCStreamer). If the branch and the target of that branch are far enough away adding a few nops in-between may actually overflow the 14 bits we have to represent the offset in the branch instruction and in that case we have to do something special and replace the branch with something else that, once again, is not a single instruction. If mayNeedRelaxation and relaxInstruction are not the way to do this is there any other better way?

That's normally something you'd handle in code generation. There's a target-independent pass in lib/CodeGen/BranchRelaxation.cpp, but it looks like PowerPC uses its own implementation in lib/Target/PowerPC/PPCBranchSelector.cpp .  Either way, the key is to ensure that the size of each instruction is computed conservatively (so it should treat your "aligned" instruction as a 64-byte instruction, since there will be 60 bytes of padding in the worst case).

-Eli

-- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

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