[llvm-dev] SETCC ISD node question (original) (raw)
Craig Topper via llvm-dev llvm-dev at lists.llvm.org
Thu Oct 25 17:20:06 PDT 2018
- Previous message: [llvm-dev] Mips :delay slot filler with store.
- Next message: [llvm-dev] SETCC ISD node question
- Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]
Should SETCC result types and input types always have the same number of vector elements or both be scalar?
I ask because it appears DAGTypeLegalizer::WidenVSELECTAndMask can create a setcc where this isn't true.
I've instrumented getNode with asserts to check the types of SETCC and I'm failing on at least these tests
LLVM :: CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll
LLVM :: CodeGen/SystemZ/vec-cmpsel.ll~Craig -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20181025/ced0e422/attachment.html>
- Previous message: [llvm-dev] Mips :delay slot filler with store.
- Next message: [llvm-dev] SETCC ISD node question
- Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]