[llvm-dev] Different SelectionDAGs for same CPU (original) (raw)

Tim Northover via llvm-dev llvm-dev at lists.llvm.org
Sat Jan 26 00:15:42 PST 2019

On Sat, 26 Jan 2019 at 00:15, Josh Sharp <mm92126 at hotmail.com> wrote:

>That C++ function is probably what looks for an FrameIndex node and >has been taught that it can be folded into the load.

How do you teach a function that a node can be folded into an instruction?

Well, if you look at the SelectAddrModeIndexed function in AArch64ISelDAGToDAG.cpp for example, at the top it checks whether the address we're selecting is an ISD::FrameIndex; if so, it converts it into an equivalent TargetFrameIndex (so that LLVM knows it's already been selected) and makes that the base of the address operand, and adds a dummy TargetConstant 0 as the offset operand; then it returns true to indicate it was able to match part of the DAG for that instruction.

Other key things to look at in that particular example is the am_indexed8 definition, which is where TableGen is taught about that C++ function (well, actually SelectAddrMode8, but that just immediately calls SelectAddrMode with an extra "8" argument), and the definition of LDRB which uses that am_indexed8 in a pattern.

The definitions are quite a maze of multiclass expansions, so I sometimes find it easier to run llvm-tblgen without a backend (from my build directory "bin/llvm-tblgen ../llvm/lib/Target/AArch64/AArch64.td -I ../llvm/include -I ../llvm/lib/Target/AArch64"). That expands everything so that you can (say) look at all the parts that make up LDRBui (the key instruction) in one place -- all of its operands and patterns and bits etc.

Cheers.

Tim.

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