[llvm-dev] [RFC] Extension to TableGen's AssemblerPredicates to support combining features with ORs (original) (raw)

Simon Cook via llvm-dev llvm-dev at lists.llvm.org
Wed Feb 19 04:24:52 PST 2020

Hi Nicolai,

On 15/02/2020 21:19, Nicolai Hähnle wrote:

This seems like an eminently reasonable feature to want to have. I'm only worried that we're moving too far along the path of having DSLs inside DSLs. I suppose the first step was already made when adding comma-separated lists there, but perhaps we can still turn back and using something more TableGen-y instead? For example, rather than "AsmCond1,AsmCond2" or "AsmCond1|AsmCond2", could we perhaps allow dag expressions that look like (and AsmCond1_ _AsmCond2) and (or AsmCond1 AsmCond2), respectively?

I agree that having DSLs inside DSLs isn't ideal, and if I were proposing adding more arbitrary combinations of operators this would be a good way of expressing it.

I suppose we can go down that road now, and still keep the limitations on the expressions already supported by the current approach. When I next have time I'll put something together see how that looks/works/feels and see which is the right route.

In the mean time does anyone have any other thoughts/preferences on which way of expressing this seems most sensible?

Thanks, Simon

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