MipsInstPrinter.cpp Source File (original) (raw)

23using namespace llvm;

25#define DEBUG_TYPE "asm-printer"

27#define PRINT_ALIAS_INSTR

28#include "MipsGenAsmWriter.inc"

30template

32 assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");

33 return MI.getOperand(OpNo).getReg() == R;

34}

37 switch (CC) {

70 }

72}

77}

82 switch (MI->getOpcode()) {

83 default:

84 break;

85 case Mips::RDHWR:

86 case Mips::RDHWR64:

87 O << "\t.set\tpush\n";

88 O << "\t.set\tmips32r2\n";

89 break;

90 case Mips::Save16:

91 O << "\tsave\t";

92 printSaveRestore(MI, STI, O);

93 O << " # 16 bit inst\n";

94 return;

95 case Mips::SaveX16:

96 O << "\tsave\t";

97 printSaveRestore(MI, STI, O);

98 O << "\n";

99 return;

100 case Mips::Restore16:

101 O << "\trestore\t";

102 printSaveRestore(MI, STI, O);

103 O << " # 16 bit inst\n";

104 return;

105 case Mips::RestoreX16:

106 O << "\trestore\t";

107 printSaveRestore(MI, STI, O);

108 O << "\n";

109 return;

110 }

111

112

114 !printAlias(*MI, Address, STI, O))

117

118 switch (MI->getOpcode()) {

119 default:

120 break;

121 case Mips::RDHWR:

122 case Mips::RDHWR64:

123 O << "\n\t.set\tpop";

124 }

125}

126

127void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,

130 if (Op.isReg()) {

132 return;

133 }

134

135 if (Op.isImm()) {

137 return;

138 }

139

140 assert(Op.isExpr() && "unknown operand kind in printOperand");

142}

143

144void MipsInstPrinter::printJumpOperand(const MCInst *MI, unsigned OpNo,

148 if (.isImm())

149 return printOperand(MI, OpNo, STI, O);

150

153 else

155}

156

158 unsigned OpNo,

162 if (.isImm())

163 return printOperand(MI, OpNo, STI, O);

164

167 if (STI.hasFeature(Mips::FeatureMips32))

168 Target &= 0xffffffff;

169 else if (STI.hasFeature(Mips::FeatureMips16))

172 } else {

174 }

175}

176

177template <unsigned Bits, unsigned Offset>

178void MipsInstPrinter::printUImm(const MCInst *MI, int opNum,

180 const MCOperand &MO = MI->getOperand(opNum);

181 if (MO.isImm()) {

187 return;

188 }

189

190 printOperand(MI, opNum, STI, O);

191}

192

193void MipsInstPrinter::printMemOperand(const MCInst *MI, int opNum,

196

197

198

199

200

201

202 switch (MI->getOpcode()) {

203 default:

204 break;

205 case Mips::SWM32_MM:

206 case Mips::LWM32_MM:

207 case Mips::SWM16_MM:

208 case Mips::SWM16_MMR6:

209 case Mips::LWM16_MM:

210 case Mips::LWM16_MMR6:

211 opNum = MI->getNumOperands() - 2;

212 break;

213 }

214

216 printOperand(MI, opNum + 1, STI, O);

217 O << "(";

218 printOperand(MI, opNum, STI, O);

219 O << ")";

220}

221

222void MipsInstPrinter::printMemOperandEA(const MCInst *MI, int opNum,

225

226

227 printOperand(MI, opNum, STI, O);

228 O << ", ";

229 printOperand(MI, opNum + 1, STI, O);

230}

231

232void MipsInstPrinter::printFCCOperand(const MCInst *MI, int opNum,

235 const MCOperand &MO = MI->getOperand(opNum);

237}

238

239void MipsInstPrinter::

242}

243

244bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,

247 bool IsBranch) {

248 OS << "\t" << Str << "\t";

249 if (IsBranch)

250 printBranchOperand(&MI, Address, OpNo, STI, OS);

251 else

252 printOperand(&MI, OpNo, STI, OS);

253 return true;

254}

255

256bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,

260 printAlias(Str, MI, Address, OpNo0, STI, OS, IsBranch);

261 OS << ", ";

262 if (IsBranch)

263 printBranchOperand(&MI, Address, OpNo1, STI, OS);

264 else

265 printOperand(&MI, OpNo1, STI, OS);

266 return true;

267}

268

271 switch (MI.getOpcode()) {

272 case Mips::BEQ:

273 case Mips::BEQ_MM:

274

275

276 return (isRegMips::ZERO(MI, 0) && isRegMips::ZERO(MI, 1) &&

277 printAlias("b", MI, Address, 2, STI, OS, true)) ||

278 (isRegMips::ZERO(MI, 1) &&

279 printAlias("beqz", MI, Address, 0, 2, STI, OS, true));

280 case Mips::BEQ64:

281

282 return isRegMips::ZERO\_64(MI, 1) &&

283 printAlias("beqz", MI, Address, 0, 2, STI, OS, true);

284 case Mips::BNE:

285 case Mips::BNE_MM:

286

287 return isRegMips::ZERO(MI, 1) &&

288 printAlias("bnez", MI, Address, 0, 2, STI, OS, true);

289 case Mips::BNE64:

290

291 return isRegMips::ZERO\_64(MI, 1) &&

292 printAlias("bnez", MI, Address, 0, 2, STI, OS, true);

293 case Mips::BGEZAL:

294

295 return isRegMips::ZERO(MI, 0) &&

296 printAlias("bal", MI, Address, 1, STI, OS, true);

297 case Mips::BC1T:

298

299 return isRegMips::FCC0(MI, 0) &&

300 printAlias("bc1t", MI, Address, 1, STI, OS, true);

301 case Mips::BC1F:

302

303 return isRegMips::FCC0(MI, 0) &&

304 printAlias("bc1f", MI, Address, 1, STI, OS, true);

305 case Mips::JALR:

306

307

308 return (isRegMips::ZERO(MI, 0) &&

309 printAlias("jr", MI, Address, 1, STI, OS)) ||

310 (isRegMips::RA(MI, 0) &&

311 printAlias("jalr", MI, Address, 1, STI, OS));

312 case Mips::JALR64:

313

314

315 return (isRegMips::ZERO\_64(MI, 0) &&

316 printAlias("jr", MI, Address, 1, STI, OS)) ||

317 (isRegMips::RA\_64(MI, 0) &&

318 printAlias("jalr", MI, Address, 1, STI, OS));

319 case Mips::NOR:

320 case Mips::NOR_MM:

321 case Mips::NOR_MMR6:

322

323 return isRegMips::ZERO(MI, 2) &&

324 printAlias("not", MI, Address, 0, 1, STI, OS);

325 case Mips::NOR64:

326

327 return isRegMips::ZERO\_64(MI, 2) &&

328 printAlias("not", MI, Address, 0, 1, STI, OS);

329 case Mips::OR:

330 case Mips::ADDu:

331

332

333 return isRegMips::ZERO(MI, 2) &&

334 printAlias("move", MI, Address, 0, 1, STI, OS);

335 default:

336 return false;

337 }

338}

339

340void MipsInstPrinter::printSaveRestore(const MCInst *MI,

343 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {

344 if (i != 0) O << ", ";

345 if (MI->getOperand(i).isReg())

347 else

348 printUImm<16>(MI, i, STI, O);

349 }

350}

351

352void MipsInstPrinter::printRegisterList(const MCInst *MI, int opNum,

355

356

357 for (int i = opNum, e = MI->getNumOperands() - 2; i != e; ++i) {

358 if (i != opNum)

359 O << ", ";

361 }

362}

static bool isReg(const MCInst &MI, unsigned OpNo)

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This class represents an Operation in the Expression.

bool print(raw_ostream &OS, DIDumpOptions DumpOpts, const DWARFExpression *Expr, DWARFUnit *U) const

WithMarkup markup(raw_ostream &OS, Markup M)

format_object< int64_t > formatHex(int64_t Value) const

void printAnnotation(raw_ostream &OS, StringRef Annot)

Utility function for printing annotations.

format_object< int64_t > formatImm(int64_t Value) const

Utility function to print immediates in decimal or hex.

bool PrintBranchImmAsAddress

If true, a branch immediate (e.g.

Instances of this class represent a single low-level machine instruction.

Instances of this class represent operands of the MCInst class.

Wrapper class representing physical registers. Should be passed by value.

Generic base class for all target subtargets.

bool hasFeature(unsigned Feature) const

void printRegName(raw_ostream &OS, MCRegister Reg) override

Print the assembler register name.

void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)

void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override

Print the specified MCInst to the specified raw_ostream.

static const char * getRegisterName(MCRegister Reg)

bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS)

StringRef - Represent a constant reference to a string, i.e.

std::string lower() const

Target - Wrapper for Target specific information.

This class implements an extremely fast bulk output stream that can only output to a stream.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

const char * MipsFCCToString(Mips::CondCode CC)

This is an optimization pass for GlobalISel generic memory operations.