RISCVMCTargetDesc.cpp Source File (original) (raw)

32#include

34#define GET_INSTRINFO_MC_DESC

35#define ENABLE_INSTR_PREDICATE_VERIFIER

36#include "RISCVGenInstrInfo.inc"

38#define GET_REGINFO_MC_DESC

39#include "RISCVGenRegisterInfo.inc"

41#define GET_SUBTARGETINFO_MC_DESC

42#include "RISCVGenSubtargetInfo.inc"

46using namespace RISCV;

48#define GET_RISCVVInversePseudosTable_IMPL

49#include "RISCVGenSearchableTables.inc"

51}

53using namespace llvm;

57 InitRISCVMCInstrInfo(X);

58 return X;

59}

63 InitRISCVMCRegisterInfo(X, RISCV::X1);

64 return X;

65}

72 unsigned SP = MRI.getDwarfRegNum(RISCV::X2, true);

76 return MAI;

77}

81 bool LargeCodeModel = false) {

84 return MOFI;

85}

89 if (CPU.empty() || CPU == "generic")

90 CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";

92 return createRISCVMCSubtargetInfoImpl(TT, CPU, CPU, FS);

93}

96 unsigned SyntaxVariant,

101}

102

106 if (TT.isOSBinFormatELF())

108 return nullptr;

109}

110

115}

116

119}

120

121namespace {

122

124 int64_t GPRState[31] = {};

125 std::bitset<31> GPRValidMask;

126

128 return Reg >= RISCV::X0 && Reg <= RISCV::X31;

129 }

130

131 static unsigned getRegIndex(MCRegister Reg) {

132 assert(isGPR(Reg) && Reg != RISCV::X0 && "Invalid GPR reg");

133 return Reg - RISCV::X1;

134 }

135

136 void setGPRState(MCRegister Reg, std::optional<int64_t> Value) {

137 if (Reg == RISCV::X0)

138 return;

139

140 auto Index = getRegIndex(Reg);

141

144 GPRValidMask.set(Index);

145 } else {

146 GPRValidMask.reset(Index);

147 }

148 }

149

150 std::optional<int64_t> getGPRState(MCRegister Reg) const {

151 if (Reg == RISCV::X0)

152 return 0;

153

154 auto Index = getRegIndex(Reg);

155

156 if (GPRValidMask.test(Index))

157 return GPRState[Index];

158 return std::nullopt;

159 }

160

161public:

162 explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)

164

165 void resetState() override { GPRValidMask.reset(); }

166

168

169

170

171

172

175 return;

176 }

177

179 default: {

180

181

182 auto NumDefs = Info->get(Inst.getOpcode()).getNumDefs();

183 for (unsigned I = 0; I < NumDefs; ++I) {

185 if (isGPR(DefReg))

186 setGPRState(DefReg, std::nullopt);

187 }

188 break;

189 }

190 case RISCV::AUIPC:

193 break;

194 }

195 }

196

200 int64_t Imm;

201 if (Size == 2)

203 else

206 return true;

207 }

208

209 if (Inst.getOpcode() == RISCV::C_JAL || Inst.getOpcode() == RISCV::C_J) {

211 return true;

212 }

213

214 if (Inst.getOpcode() == RISCV::JAL) {

216 return true;

217 }

218

219 if (Inst.getOpcode() == RISCV::JALR) {

220 if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {

222 return true;

223 }

224

225 return false;

226 }

227

228 return false;

229 }

230

233 return true;

234

236 default:

237 return false;

238 case RISCV::JAL:

239 case RISCV::JALR:

241 }

242 }

243

244 bool isCall(const MCInst &Inst) const override {

246 return true;

247

249 default:

250 return false;

251 case RISCV::JAL:

252 case RISCV::JALR:

254 }

255 }

256

259 return true;

260

262 default:

263 return false;

264 case RISCV::JALR:

267 case RISCV::C_JR:

269 }

270 }

271

274 return true;

275

276 return isBranchImpl(Inst);

277 }

278

281 return true;

282

283 return isBranchImpl(Inst);

284 }

285

288 return true;

289

291 default:

292 return false;

293 case RISCV::JALR:

296 case RISCV::C_JR:

298 }

299 }

300

301private:

302 static bool maybeReturnAddress(MCRegister Reg) {

303

304 return Reg == RISCV::X1 || Reg == RISCV::X5;

305 }

306

307 static bool isBranchImpl(const MCInst &Inst) {

309 default:

310 return false;

311 case RISCV::JAL:

313 case RISCV::JALR:

316 case RISCV::C_JR:

318 }

319 }

320};

321

322}

323

325 return new RISCVMCInstrAnalysis(Info);

326}

327

328namespace {

330 std::unique_ptr &&MAB,

331 std::unique_ptr &&MOW,

332 std::unique_ptr &&MCE) {

334 std::move(MCE));

335}

336}

337

352

353

355

358 }

359}

unsigned const MachineRegisterInfo * MRI

Analysis containing CSE Info

#define LLVM_EXTERNAL_VISIBILITY

static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")

PassInstrumentationCallbacks PIC

static MCRegisterInfo * createRISCVMCRegisterInfo(const Triple &TT)

LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC()

static MCInstPrinter * createRISCVMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)

static MCObjectFileInfo * createRISCVMCObjectFileInfo(MCContext &Ctx, bool PIC, bool LargeCodeModel=false)

static MCTargetStreamer * createRISCVNullTargetStreamer(MCStreamer &S)

static MCSubtargetInfo * createRISCVMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)

static MCTargetStreamer * createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)

static MCInstrAnalysis * createRISCVInstrAnalysis(const MCInstrInfo *Info)

static MCTargetStreamer * createRISCVAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint)

static MCInstrInfo * createRISCVMCInstrInfo()

static MCAsmInfo * createRISCVMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options)

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This class is intended to be used as a base class for asm properties and features specific to the tar...

void addInitialFrameState(const MCCFIInstruction &Inst)

static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})

.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.

Context object for machine code objects.

This is an instance of a target assembly language printer that converts an MCInst to valid target ass...

Instances of this class represent a single low-level machine instruction.

unsigned getOpcode() const

const MCOperand & getOperand(unsigned i) const

virtual bool isCall(const MCInst &Inst) const

virtual bool isBranch(const MCInst &Inst) const

virtual bool isUnconditionalBranch(const MCInst &Inst) const

virtual bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const

Given a branch instruction try to get the address the branch targets.

virtual bool isTerminator(const MCInst &Inst) const

virtual void resetState()

Clear the internal state. See updateState for more information.

virtual bool isConditionalBranch(const MCInst &Inst) const

virtual bool isReturn(const MCInst &Inst) const

virtual void updateState(const MCInst &Inst, uint64_t Addr)

Update internal state with Inst at Addr.

virtual bool isIndirectBranch(const MCInst &Inst) const

Interface to description of machine instruction set.

void initMCObjectFileInfo(MCContext &MCCtx, bool PIC, bool LargeCodeModel=false)

MCRegister getReg() const

Returns the register number.

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

Wrapper class representing physical registers. Should be passed by value.

Streaming machine code generation interface.

Generic base class for all target subtargets.

const Triple & getTargetTriple() const

Target specific streamer interface.

StringRef - Represent a constant reference to a string, i.e.

constexpr bool empty() const

empty - Check if the string is empty.

Target - Wrapper for Target specific information.

Triple - Helper class for working with autoconf configuration names.

LLVM Value Representation.

formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...

Reg

All possible values of the reg field in the ModR/M byte.

This is an optimization pass for GlobalISel generic memory operations.

MCCodeEmitter * createRISCVMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)

Target & getTheRISCV32Target()

MCAsmBackend * createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)

Target & getTheRISCV64Target()

MCELFStreamer * createRISCVELFStreamer(MCContext &C, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > MOW, std::unique_ptr< MCCodeEmitter > MCE)

static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)

RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.

static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)

RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.

static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)

RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.

static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn)

RegisterMCAsmInfo - Register a MCAsmInfo implementation for the given target.

static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)

RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.

static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)

static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)

RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.

static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)

static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)

static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)

RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.

static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)

RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.

static void RegisterMCObjectFileInfo(Target &T, Target::MCObjectFileInfoCtorFnTy Fn)

static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)