RFR: 8199138: Add RISC-V support to Zero (original) (raw)
Edward Nevill edward.nevill at gmail.com
Tue Mar 27 18:12:02 UTC 2018
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On Tue, 2018-03-27 at 17:46 +0900, John Paul Adrian Glaubitz wrote:
On 03/27/2018 05:23 PM, Edward Nevill wrote: > Sorry for the delay. I was doing another test build on qemu which takes about 3 days. > > What confuses me: Why RISCV here and not RISCV64?
In particular this hunk: @@ -1758,6 +1761,7 @@ {EMPARISC, EMPARISC, ELFCLASS32, ELFDATA2MSB, (char*)"PARISC"}, {EM68K, EM68K, ELFCLASS32, ELFDATA2MSB, (char*)"M68k"}, {EMAARCH64, EMAARCH64, ELFCLASS64, ELFDATA2LSB, (char*)"AARCH64"}, + {EMRISCV, EMRISCV, ELFCLASS64, ELFDATA2LSB, (char*)"RISCV"}, }; I know there is already 32-bit RISC-V and there are actually plans for using it. So, it looks to me you would be breaking 32-bit RISC-V here.
We could do something like
{EM_RISCV, EM_RISCV, LP64_ONLY(ELFCLASS64) NOT_LP64(ELFCLASS32),
ELFDATA2LSB, (char*)"RISCV"},Would this work?
All the best, Ed.
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