Request for reviews (XL): 7119644: Increase superword's vector size up to 256 bits (original) (raw)

Christian Thalinger christian.thalinger at oracle.com
Mon Jun 4 11:26:47 PDT 2012

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On Jun 2, 2012, at 8:19 PM, Vladimir Kozlov wrote:

Most changes after latest Tom's review were done in superword.cpp and added regression tests. I think I nailed down latest issues I had with superword code. The changes pass all testing I did. Please, review it (same web link).

src/cpu/sparc/vm/sparc.ad:

It seems Repl8B_reg_helper (and probably the other helpers too) are only used once and so is enc_repl8b. Can't we just move the code into the instruct itself using the MacroAssembler? But I guess you want to keep this change small given it's already big.

src/cpu/x86/vm/x86.ad:

• reg_def XMM0 ( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
• reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
• reg_def XMM0c( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()->next());
• reg_def XMM0d( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()->next()->next());
• reg_def XMM0e( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()->next()->next()->next());
• reg_def XMM0f( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()->next()->next()->next()->next());
• reg_def XMM0g( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()->next()->next()->next()->next()->next());
• reg_def XMM0h( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()->next()->next()->next()->next()->next()->next());

Maybe we should use a macro for this block instead of replicating it 16 times.

src/share/vm/opto/superword.cpp:

276 // Second, removed already constructed packs of the same type.

Typo "removed".

• // Reconect loads back to upper_insert_pt.

Typo.

I didn't check all the tests but I guess they are okay.

About Op_Vec names, how about using the bit size as suffix: Op_Vec32, Op_Vec64, Op_Vec128, Op_Vec256? Because most of the time when we speak about vectors it's about bit sizes like "7119644: Increase superword's vector size up to 256 bits".

-- Chris

Thanks, Vladimir On 4/3/12 10:03 AM, Vladimir Kozlov wrote: http://cr.openjdk.java.net/~kvn/7119644/webrev

7119644: Increase superword's vector size up to 256 bits Increase superword's vector size up to 256-bits for YMM AVX registers on x86. Added generation of different vector sizes for different types of arrays in the same loop. Allow to generate small (4 bytes) vectors for loops which were unrolled small number of iterations. Add new C2 types for vectors and rework VectorNode implementation. Used MachTypeNode as base node for vector mach nodes to keep vector type. Moved XMM registers definition and vector instructions into one file x86.ad (have to rename eRegI to rRegI in x8632.ad). Tested with full CTW, NSK, C2 regression tests, JPRT and added new test. Thanks, Vladimir

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