[aarch64-port-dev ] RFR (S) 8131682: C1 should use multibyte nops everywhere (original) (raw)

Andrew Haley aph at redhat.com
Mon Jul 27 12:07:12 UTC 2015

On 07/27/2015 11:53 AM, Aleksey Shipilev wrote:

On 07/27/2015 01:21 PM, Andrew Haley wrote:

On 27/07/15 10:13, Aleksey Shipilev wrote:

Thanks Goetz! Fixed the assemblerppc.inline.hpp.

Andrew/Edward, are you OK with AArch64 part? http://cr.openjdk.java.net/~shade/8131682/webrev.02/ I agree that it looks good. Please have a look to see how many NOPs take the same time as a branch. Thanks! I don't quite believe we should spend time trying branches for nops, at least for x86. The change we are discussing follows the Intel Optimization Reference Manual 3.5.1.10 "Using NOPs", which Assembler::align for x86 seems to implement with some bells and whistles. Agner agrees on using multi-byte nops (0F 1F ...) on modern x86 chips as well; up to the point he claims 4 insn/clock throughput for them.

Sure. My apologies: I responded to the wrong person. My interest is about AArch64.

Andrew.

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