pipeline class for sequence of instructions (original) (raw)

Alexeev, Alexander Alexander.Alexeev at caviumnetworks.com
Wed Jun 17 19:34:44 UTC 2015

Hello

Could somebody clarify how pipeline class is applied on sequence of instructions in architecture description file? For instance, class ialu_reg on countLeadingZerosL_bsr (snippet is below) or ialu_reg_mem on loadUB2L_immI (all from x86_64.ad). Stages for arguments read/writes, decoder and execution unit are specified only once. Is it then applied on every instructions that uses that pipeline class arguments or for the whole ins_encode body? BTW countLeadingZerosL_bsr isn't even a "single_instruction".

Class pipe_cmplt looks more reasonable, but and_cmpLTMask and cadd_cmpLTMask still don't have 4 instructions how it is defined. Why 4 cycles are allocated to decode?

Thanks, Alexander

// Integer ALU reg operation pipe_class ialu_reg(rRegI dst) %{ single_instruction; dst : S4(write); dst : S3(read); DECODE : S0; // any decoder ALU : S3; // any alu %}

instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{ predicate(!UseCountLeadingZerosInstruction); match(Set dst (CountLeadingZerosL src)); effect(KILL cr);

format %{ "bsrq dst,dst, dst,src\t# count leading zeros (long)\n\t" "jnz skip\n\t" "movl $dst, -1\n" "skip:\n\t" "negl $dst\n\t" "addl $dst, 63" %} ins_encode %{ Register Rdst = dstdstdst$Register; Register Rsrc = srcsrcsrc$Register; Label skip; __ bsrq(Rdst, Rsrc); __ jccb(Assembler::notZero, skip); __ movl(Rdst, -1); __ bind(skip); __ negl(Rdst); __ addl(Rdst, BitsPerLong - 1); %} ins_pipe(ialu_reg); %}

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