RFR: 8199138: Add RISC-V support to Zero (original) (raw)

Edward Nevill edward.nevill at gmail.com
Sun Mar 18 20:19:11 UTC 2018

On Sun, 2018-03-18 at 14:37 +0000, Andrew Haley wrote:

On 03/17/2018 07:02 PM, Edward Nevill wrote: > Webrev: http://cr.openjdk.java.net/~enevill/8199138/webrev.00 > > This webrev add Zero support for RISC-V

What happens with atomics? Do we fall back to GCC builtins for everything?

Pretty much. The only atomic operation which doesn't used GCC builtins is os::atomic_copy64. For RISC-V this just does the same as all other 64 bit CPUs.

*(jlong *) dst = *(const jlong *) src;

Interestingly, there is no implementation of atomic_copy64 for ARM32. I guess it just relies on the compiler generating LDRD/STRD correctly and doesn't support earlier ARM32 archs. I'll do a bit of investigation.

For reference here is the implementation of atomic_copy64.

Regards, Ed.

--- CUT --- static void atomic_copy64(const volatile void src, volatile void dst) { #if defined(PPC32) && !defined(SPE) double tmp; asm volatile ("lfd %0, %2\n" "stfd %0, %1\n" : "=&f"(tmp), "=Q"((volatile double)dst) : "Q"((volatile double)src)); #elif defined(PPC32) && defined(SPE) long tmp; asm volatile ("evldd %0, %2\n" "evstdd %0, %1\n" : "=&r"(tmp), "=Q"((volatile long)dst) : "Q"((volatile long)src)); #elif defined(S390) && !defined(_LP64) double tmp; asm volatile ("ld %0, 0(%1)\n" "std %0, 0(%2)\n" : "=r"(tmp) : "a"(src), "a"(dst)); #else *(jlong *) dst = *(const jlong *) src; #endif --- CUT ---

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