RFR: 8199138: Add RISC-V support to Zero (original) (raw)
John Paul Adrian Glaubitz glaubitz at physik.fu-berlin.de
Tue Mar 27 08:46:11 UTC 2018
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On 03/27/2018 05:23 PM, Edward Nevill wrote:
Sorry for the delay. I was doing another test build on qemu which takes about 3 days.
Please review the following webrev http://cr.openjdk.java.net/~enevill/8199138/webrev.02 This has the following additional changes over the previous webrev 1) Add comment in oslinux.cpp @@ -1733,6 +1733,9 @@ #ifndef EMAARCH64 #define EMAARCH64 183 /* ARM AARCH64 */ #endif +#ifndef EMRISCV /* RISCV */ + #define EMRISCV 243 +#endif
What confuses me: Why RISCV here and not RISCV64?
In particular this hunk:
@@ -1758,6 +1761,7 @@ {EM_PARISC, EM_PARISC, ELFCLASS32, ELFDATA2MSB, (char*)"PARISC"}, {EM_68K, EM_68K, ELFCLASS32, ELFDATA2MSB, (char*)"M68k"}, {EM_AARCH64, EM_AARCH64, ELFCLASS64, ELFDATA2LSB, (char*)"AARCH64"},
- {EM_RISCV, EM_RISCV, ELFCLASS64, ELFDATA2LSB, (char*)"RISCV"},
};
I know there is already 32-bit RISC-V and there are actually plans for using it. So, it looks to me you would be breaking 32-bit RISC-V here.
Adrian
--
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