[Python-Dev] Slides from today's parallel/async Python talk (original) (raw)

"Martin v. Löwis" martin at v.loewis.de
Thu Mar 14 23:56:33 CET 2013

Am 14.03.13 11:23, schrieb Trent Nelson:

ARM CPUs don't have segment registers because they have a simpler addressing model. The register CP15 came up after a couple of Google searches. Noted, thanks! Yeah that's my general sentiment too. I'm definitely curious to see if other ISAs offer similar facilities (Sparc, IA64, POWER etc), but the hierarchy will be x86/x64 > ARM > * for the foreseeable future.

Most (in particular the RISC ones) do have a general-purpose register reserved for TLS. For ARM, the interesting thing is that CP15 apparently is not available on all ARM implementations, and Linux then emulates it on processors that don't have it (by handling the trap), which is costly. Additionally, it appears that Android fails to provide that emulation (in some versions, on some processors), so that seems to be tricky ground.

Porting the PyPXCTX part is trivial compared to the work that is going to be required to get this stuff working on POSIX where none of the sublime Windows concurrency, synchronisation and async IO primitives exist.

I couldn't understand from your presentation why this is essential to your approach. IIUC, you are "just" relying on the OS providing a thread pool, (and the sublime concurrency and synchronization routines are nothing more than that, ISTM). Implementing a thread pool on top of select/poll/kqueue seems straight-forward.

Regards, Martin

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