M68HC11-Branch (Using as) (original) (raw)

9.24.6.1 Branch Improvement ¶

Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest branch instruction that reach the target. Generally these mnemonics are made by prepending ‘j’ to the start of Motorola mnemonic. These pseudo opcodes are not affected by the ‘--short-branches’ or ‘--force-long-branches’ options.

The following table summarizes the pseudo-operations.

                    Displacement Width
 +-------------------------------------------------------------+
 |                     Options                                 |
 |    --short-branches           --force-long-branches         |
 +--------------------------+----------------------------------+

Op |BYTE WORD | BYTE WORD | +--------------------------+----------------------------------+ bsr | bsr | jsr | bra | bra | jmp | jbsr | bsr jsr | bsr jsr | jbra | bra jmp | bra jmp | bXX | bXX | bNX +3; jmp | jbXX | bXX bNX +3; | bXX bNX +3; jmp | | jmp | | +--------------------------+----------------------------------+ XX: condition NX: negative of condition XX

jbsr

jbra

These are the simplest jump pseudo-operations; they always map to one particular machine instruction, depending on the displacement to the branch target.

jbXX

Here, ‘jbXX’ stands for an entire family of pseudo-operations, where XX is a conditional branch or condition-code test. The full list of pseudo-ops in this family is:

jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo jbcs jbne jblt jble jbls jbvc jbmi

For the cases of non-PC relative displacements and long displacements,as issues a longer code fragment in terms ofNX, the opposite condition to XX. For example, for the non-PC relative case:

gives