Clock input port - Name for clock input port - MATLAB (original) (raw)

Main Content

Name for clock input port

Model Configuration Pane: HDL Code Generation / Global Settings

Description

The Clock input port parameter specifies the name for the clock input port in the generated HDL code.

Settings

clk (default) | character vector

Enter the clock signal name in the generated HDL code.

For example, this code snippet shows a generated entity named my_filter when you specify this parameter as filter_clock:

ENTITY my_filter IS PORT( filter_clock : IN std_logic; clk_enable : IN std_logic; reset : IN std_logic; my_filter_in : IN std_logic_vector (15 DOWNTO 0); -- sfix16_En15 my_filter_out : OUT std_logic_vector (15 DOWNTO 0); -- sfix16_En15 ); END my_filter;

If you specify a VHDL®, Verilog®, or SystemVerilog reserved word, the code generator appends a reserved word postfix string to form a valid VHDL, Verilog, or SystemVerilog identifier. For example, if you set this parameter to the reserved wordsignal, the resulting name string issignal_rsvd.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, to set this property for a subsystem named symmetric_fir in a model named sfir_fixed, use one of these methods:

• Pass the property as an argument to the makehdl function.
  makehdl("sfir_fixed/symmetric_fir","ClockInputPort","system_clk")
• Use hdlset_param to set the parameter on the model and then generate HDL code using makehdl.
  hdlset_param("sfir_fixed","ClockInputPort","system_clk")
  makehdl("sfir_fixed/symmetric_fir")

Programmatic Use

Version History

Introduced in R2012a