Entity conflict postfix - Text to resolve duplicate module names - MATLAB (original) (raw)

Main Content

Text to resolve duplicate module names

Model Configuration Pane: Global Settings / General

Description

Specify the text as a character vector to resolve duplicate VHDL® entity, Verilog® or SystemVerilog module names in generated code.

Settings

_block (default) | character vector

Default: _block

The specified postfix resolves duplicate VHDL entity, Verilog or SystemVerilog module names.

For example, if HDL Coder™ detects two entities with the nameMyFilter, the code generator names the first entityMyFilter and the second entityMyFilter_block.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify this property when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

• Pass the property as an argument to the makehdl function.
  makehdl('sfir_fixed/symmetric_fir', ...
  'EntityConflictPostfix','_entity')
• When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
  hdlset_param('sfir_fixed','EntityConflictPostfix','_entity')
  makehdl('sfir_fixed/symmetric_fir')

Recommended Settings

No recommended settings.

Programmatic Use

Version History

Introduced in R2012a