Reset input port - Name for reset input port - MATLAB (original) (raw)

Name for reset input port

Model Configuration Pane: Global Settings

Description

Enter the name for the reset input port in generated HDL code.

Dependencies

If you specify active-high for Reset asserted level, the reset input signal is asserted active-high. To reset the registers in the entity, the input value to the Reset input port must be high. If you specify active-low for Reset asserted level, the reset input signal is asserted active-low. To reset the registers in the entity, the input value to the Reset input port must be low.

Settings

reset (default) | character vector

Default: reset

Enter a character vector for the reset input port name in generated HDL code.

For example, if you override the default with 'chip_reset' for the generating system myfilter, the generated entity declaration might look as follows:

ENTITY myfilter IS PORT( clk : IN std_logic; clk_enable : IN std_logic; chip_reset : IN std_logic; myfilter_in : IN std_logic_vector (15 DOWNTO 0); myfilter_out : OUT std_logic_vector (15 DOWNTO 0); ); END myfilter;

If you specify a VHDL®, Verilog® or SystemVerilog reserved word, the code generator appends a reserved word postfix string to form a valid VHDL, Verilog or SystemVerilog identifier. For example, if you specify the reserved word signal, the resulting name string would be signal_rsvd.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify sync as the ResetType when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

No recommended settings.

Programmatic Use

Parameter: ResetInputPort
Type: character vector
Value: A valid identifier in the target language
Default: 'reset'

Version History

Introduced in R2012a