Choose a Test Bench for Generated HDL Code - MATLAB & Simulink (original) (raw)
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When you generate HDL code with HDL Coder™, you can optionally generate a test bench as well. The code generator also generates build-and-run scripts for the HDL simulator you specify. The test bench options are:
- HDL test bench — An HDL test bench that includes the generated HDL DUT and files containing input and output data vectors. This test bench verifies the generated HDL DUT against test vectors generated from your Simulink® model. See Test Bench Generation.
- Cosimulation model — A Simulink model that includes an HDL Cosimulation block that runs your generated HDL code in an HDL simulator. The model also includes your original Simulink stimulus generation, your behavioral model, and any blocks for display or analysis of the output data. The model compares the output of the HDL Cosimulation block against the output of the source subsystem. See Generate Cosimulation Model.
- SystemVerilog DPI test bench — An HDL test bench that includes the generated HDL DUT and a generated C-language component. The C component creates input stimuli and runs a behavioral model of the DUT subsystem. The test bench uses a direct programming interface (DPI) to run the C component inside an HDL simulation. This test bench verifies the generated HDL DUT against a C representation of the source Simulink model. See Verify HDL Design Using SystemVerilog DPI Test Bench.
- FPGA-in-the-loop — A Simulink model that includes an FPGA-in-the-Loop block that communicates with your HDL design while it runs on the FPGA board. The model also includes your original Simulink stimulus generation, your behavioral model, and any blocks for display or analysis of the output data. The model compares the output of the FPGA-in-the-Loop block against the output of the source subsystem. See FIL Simulation with HDL Workflow Advisor for Simulink (HDL Verifier).
Select test bench options in HDL Workflow Advisor under > , or in the Model Configuration Parameters dialog box, under > . Alternatively, for command-line access, select your test bench using the properties of makehdltb.
For FPGA-in-the-loop, select the target workflow in HDL Workflow Advisor underSet Target > Set Target Device and Synthesis Tool. Then select your FPGA and synthesis tool. You can also generate an FPGA-in-the-loop model for existing HDL code by using FPGA-in-the-Loop Wizard (HDL Verifier).
| Test Bench | License Requirements | Pros | Cons |
|---|---|---|---|
| HDL test bench | Fast compile time in HDL simulator | Runs simulation to generate data files, which can take a long time for large data setsFile I/O can slow down simulation for large data setsRun test in HDL simulatorFixed input stimulus | |
| Cosimulation model | HDL Verifier™ | Fast compile time in HDL simulatorRun tests from Simulink, including changing parameters to affect input stimulusAutomatic test bench execution from HDL Workflow Advisor | |
| SystemVerilog DPI test bench | HDL VerifierSimulink Coder™ | Fast generation time because the code generator does not run a simulationFast simulation time for large data sets, because the stimulus comes from generated code rather than files | Run test in HDL simulatorNo tunable parameters in stimulus generation |
| FPGA-in-the-loop | HDL VerifierHDL Verifier Support Package for AMD FPGA and SoC Devices or HDL Verifier Support Package for Intel® FPGA Boards | Run tests from Simulink, including changing parameters to affect input stimulusPrototype hardware implementation of your DUT | Long generation time due to synthesis into FPGAHardware setup |