AMD FPGA and SoC Devices - MATLAB & Simulink (original) (raw)

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Deploy generated HDL code on AMD® FPGA, Zynq, Versal and RFSoC Devices

HDL Coder™ can generate an IP core, integrate it into your Vivado® project, and program the AMD hardware. To deploy your design to the AMD hardware, you must install the HDL Coder Support Package for AMD FPGA and SoC Devices. For installation information, see HDL Coder Supported Hardware.

HDL Coder Support Package for AMD FPGA and SoC Devices supports the generation of IP cores that can be integrated into FPGA designs using Xilinx® Vivado. When used in combination with Embedded Coder®, this solution can program the AMD Zynq® SoC using C and HDL code generation. The hardware-software co-design workflow spans simulation, prototyping, verification, and implementation. Using Embedded Coder, you can generate and build the embedded software, and run it on the ARM® processor. See Hardware-Software Co-Design Workflow for SoC Platforms.

For more information on tool and board support, see Supported EDA Tools and Hardware.

Categories

• Setup and Configuration
  Download and install support package for use with third-party EDA tools and supported hardware
• Get Started with Hardware-Software Co-Design
  Deploy generated HDL code on a target hardware platform
• Generate an IP Core and Bitstream
  Generate HDL IP core and bitstream that contain HDL code for deployment on standalone AMD FPGA boards and SoC Devices
• Target AMD RFSoC Hardware
  Run your MATLAB® or Simulink® algorithm on the AMD RFSoC target hardware

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