Alex Dickinson | University of Adelaide (original) (raw)
Papers by Alex Dickinson
IEEE Journal of Solid-state Circuits, 1996
The constrained data access patterns occurring within memory-based packet switches permit the des... more The constrained data access patterns occurring within memory-based packet switches permit the design of application specific SRAM devices that may outperform generic SRAM parts in switch applications. We describe two such devices: one reads and writes a single location in a single 10 ns cycle; the other uses a systolic approach to pipeline accesses in a large array resulting in
Proposes a scalable memory architecture that maintains a high data rate, independent of address s... more Proposes a scalable memory architecture that maintains a high data rate, independent of address sequence and memory size. It is suitable for applications where throughput is of primary importance and access latency is tolerable. A rectangular array of memory blocks is pipelined to build a memory with an operating frequency determined only by the access time of a single block. This is independent of the number of blocks because address and data communication is localized to adjacent memory blocks. Rather than sacrificing speed for memory size, the new approach scales to provide high-throughput random access memories of very large size with some increase in latency
Page 1. Adiabatic Computing with the 2N-2N2D Logic Family Alan Kramer, John S. Denker, Stephen C.... more Page 1. Adiabatic Computing with the 2N-2N2D Logic Family Alan Kramer, John S. Denker, Stephen C. Avery, Alex G. Dickinson, and Thomas R. Wik AT&T Bell Laboratories Holmdel, NJ 07733 Introduction Low-energy computing is an idea whose time has come. ...
With adiabatic techniques for capacitor charging, theory suggests that it should be possible to b... more With adiabatic techniques for capacitor charging, theory suggests that it should be possible to build gates with arbitrarily small energy dissipation. In practice the complexity of adiabatic approaches has made them impractical. We describe a new CMOS logic family-Adiabatic Dynamic Logic (ADL)-that is the result of combining adiabatic theory with conventional CMOS dynamic logic. ADL gates are simple, general, readily cascadable, and may be fabricated in a standard CMOS process. Simulation and fabrication test results indicating that ADL offers an order of magnitude reduction in power consumption over conventional CMOS circuitry
IEEE Journal of Solid-state Circuits, 1995
A 256 X 256 CMOS photo-gate active pixel image sensor is presented. The image sensor uses four MO... more A 256 X 256 CMOS photo-gate active pixel image sensor is presented. The image sensor uses four MOS transistors within each pixel to buffer the photo-signal, enhance sensitivity, and suppress noise. The pixel size is 20 micrometers X 20 micrometers and was implemented in a standard digital 0.9 micrometers single-polysilicon, double-metal, n-well CMOS process; leading to 25% fill-factor. Row and column decoders and counters are monolithically integrated as well as per column analog signal correlated double-sampling (CDS) processors, yielding a total chip size of approximately 4.5 mm X 5.0 mm. The image sensor features random accessibility and can be employed for electronic panning applications. It is powered from a single 5.0 V source. At 5.0 V power supply, the video signal saturation level is approximately 1,200 mV with rms read-out noise level of approximately 300 (mu) V, yielding a dynamic range of 72 dB (12 bits). The read-out sensitivity is approximately 6.75 (mu) V per electron, indicating a read-out node capacitance of approximately 24 fF which is consistent with the extracted value. The measured dark current (at room temperature) is approximately 160 mV/s, equivalent to 3.3 nA/cm2. The raw fixed pattern noise (exhibited as column-wise streaks) is approximately 20 mV (peak-to-peak) or approximately 1.67% of saturation level. At 15 frames per second, the power dissipation is approximately 75 mW.
IEEE Journal of Solid-state Circuits, 1996
The constrained data access patterns occurring within memory-based packet switches permit the des... more The constrained data access patterns occurring within memory-based packet switches permit the design of application specific SRAM devices that may outperform generic SRAM parts in switch applications. We describe two such devices: one reads and writes a single location in a single 10 ns cycle; the other uses a systolic approach to pipeline accesses in a large array resulting in
Proposes a scalable memory architecture that maintains a high data rate, independent of address s... more Proposes a scalable memory architecture that maintains a high data rate, independent of address sequence and memory size. It is suitable for applications where throughput is of primary importance and access latency is tolerable. A rectangular array of memory blocks is pipelined to build a memory with an operating frequency determined only by the access time of a single block. This is independent of the number of blocks because address and data communication is localized to adjacent memory blocks. Rather than sacrificing speed for memory size, the new approach scales to provide high-throughput random access memories of very large size with some increase in latency
Page 1. Adiabatic Computing with the 2N-2N2D Logic Family Alan Kramer, John S. Denker, Stephen C.... more Page 1. Adiabatic Computing with the 2N-2N2D Logic Family Alan Kramer, John S. Denker, Stephen C. Avery, Alex G. Dickinson, and Thomas R. Wik AT&T Bell Laboratories Holmdel, NJ 07733 Introduction Low-energy computing is an idea whose time has come. ...
With adiabatic techniques for capacitor charging, theory suggests that it should be possible to b... more With adiabatic techniques for capacitor charging, theory suggests that it should be possible to build gates with arbitrarily small energy dissipation. In practice the complexity of adiabatic approaches has made them impractical. We describe a new CMOS logic family-Adiabatic Dynamic Logic (ADL)-that is the result of combining adiabatic theory with conventional CMOS dynamic logic. ADL gates are simple, general, readily cascadable, and may be fabricated in a standard CMOS process. Simulation and fabrication test results indicating that ADL offers an order of magnitude reduction in power consumption over conventional CMOS circuitry
IEEE Journal of Solid-state Circuits, 1995
A 256 X 256 CMOS photo-gate active pixel image sensor is presented. The image sensor uses four MO... more A 256 X 256 CMOS photo-gate active pixel image sensor is presented. The image sensor uses four MOS transistors within each pixel to buffer the photo-signal, enhance sensitivity, and suppress noise. The pixel size is 20 micrometers X 20 micrometers and was implemented in a standard digital 0.9 micrometers single-polysilicon, double-metal, n-well CMOS process; leading to 25% fill-factor. Row and column decoders and counters are monolithically integrated as well as per column analog signal correlated double-sampling (CDS) processors, yielding a total chip size of approximately 4.5 mm X 5.0 mm. The image sensor features random accessibility and can be employed for electronic panning applications. It is powered from a single 5.0 V source. At 5.0 V power supply, the video signal saturation level is approximately 1,200 mV with rms read-out noise level of approximately 300 (mu) V, yielding a dynamic range of 72 dB (12 bits). The read-out sensitivity is approximately 6.75 (mu) V per electron, indicating a read-out node capacitance of approximately 24 fF which is consistent with the extracted value. The measured dark current (at room temperature) is approximately 160 mV/s, equivalent to 3.3 nA/cm2. The raw fixed pattern noise (exhibited as column-wise streaks) is approximately 20 mV (peak-to-peak) or approximately 1.67% of saturation level. At 15 frames per second, the power dissipation is approximately 75 mW.