Atanas N Parashkevov | The University of Adelaide (original) (raw)

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Papers by Atanas N Parashkevov

Research paper thumbnail of ARC - A Verification Tool for Concurrent Systems

Research paper thumbnail of Space efficient reachability analysis through use of pseudo-root states

Lecture Notes in Computer Science, 1997

. This paper presents a novel reachability analysis techniquewhich, while still maintaining a set... more . This paper presents a novel reachability analysis techniquewhich, while still maintaining a set of reached states, significantly reducesthe size of this set through excluding a specific subset of those states,referred to as pseudo-root states. Pseudo-root states are states whichare not reachable from the unexplored state space of the finite model.Such states may be safely discarded from state storage. The

Research paper thumbnail of ARC-a tool for efficient refinement and equivalence checking for CSP

Proceedings of 1996 IEEE Second International Conference on Algorithms and Architectures for Parallel Processing, ICA/sup 3/PP '96, 1996

Research paper thumbnail of An automated method for test model generation from switch level circuits

Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC, 2003

Custom VLSI design at the switch level is commonly applied when a chip is required to meet string... more Custom VLSI design at the switch level is commonly applied when a chip is required to meet stringent operating requirements in terms of speed, power, or area. ATPG requires gate level models, which are verified for correctness against switch level models. Typically, test models are created manually from the switch level models-a tedious, error-prone process requiring experienced DFT engineers. This paper presents an automated flow for creating gate level test models from circuits at the switch level. The proposed flow utilizes Motorola's Switch Level Verification (SLV) tool, which employs detailed switch level analysis to model the behavior of MOS transistors and represent them at a higher level of abstraction. We present experimental results, which demonstrate that the automated flow is capable of producing gate models that meet the ATPG requirements and are comparable to manually created ones.

Research paper thumbnail of Automated equivalence checking of switch level circuits

Proceedings of the 39th conference on Design automation - DAC '02, 2002

A chip that is required to meet strict operating criteria in terms of speed, power, or area is co... more A chip that is required to meet strict operating criteria in terms of speed, power, or area is commonly custom designed at the switch level. Traditional techniques for verifying these designs, based on simulation, are expensive in terms of resources and cannot completely guarantee correct operation. Formal verification methods, on the other hand, provide for a complete proof of correctness, and require less effort to setup. This paper presents Motorola's Switch Level Verification (SLV) tool, which employs detailed switch level analysis to model the behavior of MOS transistors and obtain an equivalent RTL model. This tool has been used for equivalence checking at the switch level for several years within Motorola for the PowerPC, M*Core and DSP custom blocks. We focus on the novel techniques employed in SLV, particularly in the areas of pre-charged and sequential logic analysis, and provide details on the automated and integrated equivalence checking flow in which the tool is used.

Research paper thumbnail of A software test program generator for verifying system-on-chips

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005., 2005

Design verification is crucial for successful systemson-chips (SoCs). However, validating and pro... more Design verification is crucial for successful systemson-chips (SoCs). However, validating and proving the correctness of SoCs is often a bottleneck in the design project. This paper presents a novel technique to test the SoC at the system level using software application based programs. Our Software Application Level Verification Methodology (SALVEM) employs test programs composed of dynamic sequences of software code segments. The SALVEM system implements a test generator to create these software test programs automatically. Experiments were conducted applying SALVEM tests to the Altera Nios SoC. A feedback verification flow is also feasible in our SALVEM system. SALVEM test runs are analyzed to direct the test generator toward important SoC scenarios.

Research paper thumbnail of Coverage measurement for software application testing using partially ordered domains and symbolic trajectory evaluation techniques

Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06), 2006

ABSTRACT

Research paper thumbnail of Coverage Measurement for Software Application Level Verification using Symbolic Trajectory Evaluation Techniques

Second IEEE International Workshop on Electronic Design, Test and Applications, 2004

a bottleneck for hardware design projects. A new solution is a design verification methodology th... more a bottleneck for hardware design projects. A new solution is a design verification methodology that applies coverage driven verification at the embedded software application level. This methodology currently lacks an appropriate coverage measurement technique. This paper proposes a new coverage model for the software application level. Using this coverage model, a novel technique to represent and measure coverage is described. This technique uses ideas such as control graph structures and checking algorithms to estimate the completeness of software application verification.

Research paper thumbnail of ARC - A Verification Tool for Concurrent Systems

Research paper thumbnail of Space efficient reachability analysis through use of pseudo-root states

Lecture Notes in Computer Science, 1997

. This paper presents a novel reachability analysis techniquewhich, while still maintaining a set... more . This paper presents a novel reachability analysis techniquewhich, while still maintaining a set of reached states, significantly reducesthe size of this set through excluding a specific subset of those states,referred to as pseudo-root states. Pseudo-root states are states whichare not reachable from the unexplored state space of the finite model.Such states may be safely discarded from state storage. The

Research paper thumbnail of ARC-a tool for efficient refinement and equivalence checking for CSP

Proceedings of 1996 IEEE Second International Conference on Algorithms and Architectures for Parallel Processing, ICA/sup 3/PP '96, 1996

Research paper thumbnail of An automated method for test model generation from switch level circuits

Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC, 2003

Custom VLSI design at the switch level is commonly applied when a chip is required to meet string... more Custom VLSI design at the switch level is commonly applied when a chip is required to meet stringent operating requirements in terms of speed, power, or area. ATPG requires gate level models, which are verified for correctness against switch level models. Typically, test models are created manually from the switch level models-a tedious, error-prone process requiring experienced DFT engineers. This paper presents an automated flow for creating gate level test models from circuits at the switch level. The proposed flow utilizes Motorola's Switch Level Verification (SLV) tool, which employs detailed switch level analysis to model the behavior of MOS transistors and represent them at a higher level of abstraction. We present experimental results, which demonstrate that the automated flow is capable of producing gate models that meet the ATPG requirements and are comparable to manually created ones.

Research paper thumbnail of Automated equivalence checking of switch level circuits

Proceedings of the 39th conference on Design automation - DAC '02, 2002

A chip that is required to meet strict operating criteria in terms of speed, power, or area is co... more A chip that is required to meet strict operating criteria in terms of speed, power, or area is commonly custom designed at the switch level. Traditional techniques for verifying these designs, based on simulation, are expensive in terms of resources and cannot completely guarantee correct operation. Formal verification methods, on the other hand, provide for a complete proof of correctness, and require less effort to setup. This paper presents Motorola's Switch Level Verification (SLV) tool, which employs detailed switch level analysis to model the behavior of MOS transistors and obtain an equivalent RTL model. This tool has been used for equivalence checking at the switch level for several years within Motorola for the PowerPC, M*Core and DSP custom blocks. We focus on the novel techniques employed in SLV, particularly in the areas of pre-charged and sequential logic analysis, and provide details on the automated and integrated equivalence checking flow in which the tool is used.

Research paper thumbnail of A software test program generator for verifying system-on-chips

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005., 2005

Design verification is crucial for successful systemson-chips (SoCs). However, validating and pro... more Design verification is crucial for successful systemson-chips (SoCs). However, validating and proving the correctness of SoCs is often a bottleneck in the design project. This paper presents a novel technique to test the SoC at the system level using software application based programs. Our Software Application Level Verification Methodology (SALVEM) employs test programs composed of dynamic sequences of software code segments. The SALVEM system implements a test generator to create these software test programs automatically. Experiments were conducted applying SALVEM tests to the Altera Nios SoC. A feedback verification flow is also feasible in our SALVEM system. SALVEM test runs are analyzed to direct the test generator toward important SoC scenarios.

Research paper thumbnail of Coverage measurement for software application testing using partially ordered domains and symbolic trajectory evaluation techniques

Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06), 2006

ABSTRACT

Research paper thumbnail of Coverage Measurement for Software Application Level Verification using Symbolic Trajectory Evaluation Techniques

Second IEEE International Workshop on Electronic Design, Test and Applications, 2004

a bottleneck for hardware design projects. A new solution is a design verification methodology th... more a bottleneck for hardware design projects. A new solution is a design verification methodology that applies coverage driven verification at the embedded software application level. This methodology currently lacks an appropriate coverage measurement technique. This paper proposes a new coverage model for the software application level. Using this coverage model, a novel technique to represent and measure coverage is described. This technique uses ideas such as control graph structures and checking algorithms to estimate the completeness of software application verification.